Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 94-95

  Bansal, Aditya ^a   Paul, Bipul C ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN INDUCED BARRIER LOWERING (DIBL); FRINGING CAPACITANCE; GATE CAPACITANCE; GATE TUNNELING CURRENT; ULTRATHIN BODY DOUBLE GATE (DGMOS) DEVICES;

CAPACITANCE; COMPUTER SIMULATION; DELAY CIRCUITS; FUNCTIONS; GATES (TRANSISTOR); LEAKAGE CURRENTS; OSCILLATORS (ELECTRONIC); THRESHOLD VOLTAGE;

MOS DEVICES;

EID: 13344249129     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J.G. Fossum, et. al., pp. 679-682, IEDM'03.
2. Taurus-DS, version 2003.06, Synopsys Inc.
3. K. Nose, et. al., pp. 228-230, ISLPED'00.
4. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press.
5. Y.-K. Choi, et. al., pp. 436-441, IEEE TED, March 2002.
6. W. Quan, et. al., pp. 889-894, IEEE TED, May 2002.