Information-driven circuit synthesis with the pre-characterized gate libraries

Journal of Systems Architecture

Volumn 51, Issue 6-7, 2005, Pages 405-423

  Jóźwiak, Lech ^a   Biegański, Szymon ^a   Chojnacki, Artur ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; DECISION TABLES; DIGITAL LIBRARIES; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC GATES; MATHEMATICAL MODELS; MICROELECTRONICS; TABLE LOOKUP;

CIRCUIT SYNTHESIS; MICROELECTRONIC TECHNOLOGY; REDUCED ORDERED BINARY DECISION DIAGRAMS (ROBDD); SYMMETRIC FUNCTIONS;

ELECTRIC NETWORK ANALYSIS;

EID: 19744362077     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2004.07.003     Document Type: Conference Paper

References (47)

1. R.L. Ashenhurst, The decomposition of switching functions, in: Proceedings of International Symposium on the Theory of Switching Functions, pp. 74-116, April 1959.
2. V. Bertacco, M. Damiani, The disjunctive decomposition of logic functions, in: Proc. of the IEEE/ACM International Conference on Computer-Aided Design, 1997, pp. 78-82.
3. J. Brzozowski, T. Łuba, Decomposition of Boolean Functions Specified by Cubes, University of Waterloo Research Report, CS-97-01, Waterloo, Canada, January (revised October 1998), 1997.
4. S.-C. Chang, M. Marek-Sadowska, Technology mapping via transformations of functional graphs, in: Proceedings of the IEEE International Conference on Computer Design, 1992, Cambridge, MA, pp. 159-162.
5. A. Chojnacki, L. Jóźwiak, Multi-valued sub-function encoding in functional decomposition based on information relationship measures, in: 30th IEEE International Symposium on Multiple-valued Logic, ISMVL '2000.
6. H.A. Curtis A generalized tree circuits Journal of the Association for Computing Machinery 8 1961 484 496
7. K. Eckl, C. Legl, B. Wurth, An implicit approach to functional decomposition of incompletely specified Boolean functions, in: Proc. of the International Workshop on Logic and Synthesis IWLS'97, 1997.
8. M. Fujita, Y. Masunaga, and M. Ciesielski Logic Synthesis and Verification 2002 Kluwer Academic Publishers Ch. Multi-level logic optimization
9. J. Hartmanis, and R. Stearns Algebraic Structure Theory of Sequential Machines 1966 Prentice-Hall Englewood Cliffs, NJ
10. L. Jóźwiak General decomposition and its use in digital circuit synthesis VLSI Design 3 3 1995
11. L. Jóźwiak, Information relationships and measures-an analysis apparatus for efficient information system synthesis, in: 23rd EUROMICRO Conference, Budapest, Hungary, September 1-4, 1997, IEEE Computer Society Press, pp. 13-23.
12. L. Jóźwiak, Information relationship measures in application to logic design, in: IEEE International Symposium on Multiple-Valued Logic, Freiburg Im Breisgan, Germany, May 20-22, 1998.
13. L. Jóźwiak, A. Chojnacki, Functional decompsition based on information relationship measures extremely effective for symmetric functions, in: 25th EUROMICRO Conference, Milan, Italy, September 8-10, 1999, ISBN 0-7695-0321-7, IEEE Computer Society Press, Los Alamitos, CA, 1999, pp. 150-160.
14. L. Jóźwiak, A. Chojnacki, High-quality sub-function construction in functional decomposition based on information relationship measures, DATE'2001-Design, Automation and Test in Europe, Munich, Germany, March 13-16, 2001, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 383-390.
15. L. Jóźwiak, A. Chojnacki, Effective and efficient FPGA synthesis through functional decomposition based on information relationship measures, in: DSD'2001-Euromicro Symposium on Digital System Design, September 4-6, 2001, Warsaw, Poland, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 30-37.
16. L. Jóźwiak, and A. Chojnacki Effective and efficient combinational circuit synthesis for the fpga-based reconfigurable systems Special Issue of Journal of Systems Architecture on Reconfigurable Computing 49 4-6 2003 247 265
17. L. Jóźwiak, P. Konieczny, Input support minimization for efficient PLD and FPGA synthesis, in: International Workshop on Logic and Architecture Synthesis (IWLAS'96), 1996, pp. 30-37.
18. L. Jóźwiak, A. Ślusarczyk, and A. Chojnacki Fast and compact sequential circuits for the fpga-based reconfigurable systems Special Issue of Journal of Systems Architecture on Reconfigurable Computing 49 4-6 2003 227 246
19. L. Jóźwiak, and A. Ślusarczyk General decomposition of incompletely specified sequential machines with multi-state behaviour realisation Journal of Systems Architecture 50 8 2004 445 492
20. L. Jóźwiak, F. Volf, An efficient method for decomposition of multiple output Boolean functions and assigned sequential machines, in: Proc, EDAC-The European Conference on Design Automation, Brussels, Belgium, 1992, pp. 114-122.
21. V.N. Kravets, K.A. Sakallah, Constructive library-aware synthesis using symmetries, in: DATE'2000 Conference, Paris, France, March 27-30, 2000, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 208-213.
22. Y.-T. Lai, M. Padram, S. Vrudhula, BDD-based decomposition of logic functions with application to FPGA synthesis, in: ACM/IEEEE Design Automation Conference, 1993, pp. 642-647.
23. Y.-T. Lai, K.-R.R. Pan, and M. Pedram OBDD-based function decomposition: algorithms and implementation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15 1996 977 990 Aug
24. C. Legl, B. Wurth, and K. Eckl Computing support-minimal subfunctions during functional decomposition IEEE Transactions on Very Large Scale Integration [VLSI] Systems 6 3 1998 354 363
25. T. Łuba et al., Combining serial decomposition with topological partitioning for effective multi-level pla implementations, in: Proc. IFIP Working Conference on Logic and Architecture Synthesis, 1990, pp. 77-86.
26. S. Minato, G. De Michelli, Finding all simple disjunctive decompositions using irredundant sum-of-products forms, in: Proc. of the IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 111-117.
27. R.H. M-tfing Algorithmic aspects of the substitution decomposition in optimization over relations, set systems and Boolean functions Annals of Operations Research 4 1985 195 225
28. M. Perkowski, M. Marek-Sadowska, L. Jóźwiak, T. Łuba, S. Grygiel, M. Nowicka, R. Malvi, Z. Wang, S. Zhang, Decomposition of multiple-valued relations, in: Proc. International Symposium on Multiple-Valued Logic, 1997, pp. 13-18.
29. G.N. Povarov On functional separability of boolean functions Lectures of the USSR Academy of Sciencies 44 5 1954
30. M. Rawski, L. Jóźwiak, T. Łuba, The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition, in: 25th EUROMICRO Conference, Milan, Italy, September 1999.
31. M. Rawski, L. Jóźwiak, and T. Łuba Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures Journal of Systems Architecture 2 47 2001 137 155
32. J.P. Roth, and R.M. Karp Minimization over Boolean Graphs IBM Journal of Research and Development 23 April 1962
33. R. Rzechowski, L. Jóźwiak, T. Łuba, Technology driven multilevel logic synthesis based on functional decomposition into gates, in: 25th EUROMICRO Conference, Milan, Italy, September 1999, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 368-375.
34. T. Sasao Logic Synthesis for VLSI Design 1993 Kluwer Academic Publishers Ch. FPGA design by generalized functional decomposition
35. H. Sawada, T. Suyama, A. Nagoya, Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization, in: Proc. of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'95), 1995, pp. 355-358.
36. H. Sawada, T. Suyama, and A. Nagoya Logic Synthesis for look-up table based FPGAs using functional decomposition and Boolean resubsitution IEICE Transactions on Information and Systems E80-D 10 1997 1017 1023
37. C. Scholl Multi-output functional decomposition with exploitation of don't cares Design, Automation and Test in Europe 1998 743 748
38. E.M. Sentovich et al., SIS: A System for Sequential Circuit Synthesis, Electronic Research Laboratory, University of California, Berkeley, Memorandum No. UCB/ERL M92/41, May 1992.
39. C.E. Shannon The synthesis of two-terminal switching circuits The Bell Systems Technology Journal 28 1 1949 59
40. W.-Z Shen., J.-D Huang, S.-M Chao, Lambda Set Selection in Roth-Karp Decomposition for LUT-based FPGA Technology Mapping, in: 32nd ACM/IEEE Design Automation Conference, 1995.
41. T. Stanion, C. Sechen, A method for finding good Ashenhurst decomposition and its application to FPGA synthesis, in: Proceedings of the ACM/IEEE Design Automation Conference, 1995, San Francisco, CA, pp. 60-64.
42. F. Volf, L. Jóźwiak, Decompositional logic synthesis approach for look up table based fpgas, in: Proc. 8th IEEE International ASIC Conference, Austin, Texas, 1995.
43. F. Volf, L. Jóźwiak, and M. Stevens Division-based versus general decomposition-based multiple-level logic synthesis VLSI Design 3 3 1995 267 287
44. B. Wurth, U. Schlichtmann, K. Eckl, and K.J. Antreich Functional multiple-output decomposition with application to technology mapping for look-up table based FPGAs ACM Transactions on Design Automation of Electronic Systems 4 3 1999
45. S. Yamashita, H. Sawada, A. Nagoya, New methods to find optimal non-disjoint bi-decomposition, in: Proceedings of Design Automation Conference, 1998, pp. 59-68.
46. C. Yang, and M. Ciesielski Bds: a bdd-based logic optimization system Transitions on Computer-Aided Design of Integrated Systems and Circuits 21 2002 866 876
47. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, http://www.cbl.ncsu.edu/.