General decomposition of incompletely specified sequential machines with multi-state behavior realization

Journal of Systems Architecture

Volumn 50, Issue 8, 2004, Pages 445-492

  Jóźwiak, Lech ^a   Ślusarczyk, Aleksander ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; IMAGE CODING; KNOWLEDGE ENGINEERING; LARGE SCALE SYSTEMS; LEARNING SYSTEMS; LOGIC GATES; MATHEMATICAL MODELS; NEURAL NETWORKS; SYSTEMS ENGINEERING; VLSI CIRCUITS;

DECOMPOSITION STRUCTURES; DISCRETE FUNCTIONS; GENERAL DECOMPOSITION;

SEQUENTIAL MACHINES;

EID: 3042826126     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2003.11.002     Document Type: Article

References (67)

1. M. Burns, M. Perkowski, L. Jóźwiak, An efficient approach to decomposition of multi-output boolean functions with large sets of bound variables, in: Proceedings of EUROMICRO-98 Conference, Vasteras, Sweden, 1998, pp. 16-23.
2. G. Files, M. Perkowski, Multi-valued functional decomposition as machine learning method, in: Proceedings of ISMVL'98, Fukuoka, Japan, 1998, pp. 173-178.
3. Lin T., Cercone N. (Eds.), Rough Sets and Data Mining - Analysis of Impresise Data. 1997;Kluwer, Dordrecht.
4. T. Luba, Decomposition of multiple-valued functions, in: Proceedings of IEEE ISMVL'95, Bloomington, Indiana, USA, 1995.
5. Luba T., Rybnik J. Rough sets and some aspects of logic synthesis. Slowinski R. Intelligent Decision Support - Handbook of Applications and Advances of the Rough Sets Theory. 1993;Kluwer, Dordrecht.
6. T. Ross, M. Noviskey, T. Taylor, D. Gadd, Pattern theory: an engineering paradigm for algorithm design, Final Technical Report, Wright Laboratories, WL/AART/WPAFB, 1991.
7. H. Selvaraj, H. Niewiadomski, M. Pleban, P. Sapiecha, Decomposition of digital circuits and neural networks, in: Proceedings of Special Sessions on Modern Digital System Synthesis at The Fifth Multi-Conference on Systemics, Cybernetics and Informatics-SCI'2001, Orlando, USA, 2001, pp. 302-307.
8. M. Venkatesan, H. Selvaraj, R. Bignall, Character recognition using functional decomposition, in: Proceedings of International Conference on Computational Intelligence and Multimedia Applications, 1998, pp. 721-726.
9. Ashar P., Devadas S., Newton A. Sequential Logic Synthesis. 1992;Kluwer, Boston/Dordrecht/London.
10. J. Brzozowski, T. Luba, Decomposition of Boolean functions specified by cubes, University of Waterloo Research Report, CS-97-01, Waterloo, Canada, January (revised October 1998), 1997.
11. M. Burns, M. Perkowski, S. Grygiel, L. Jóźwiak, An efficient and effective approach to column-based input/output encoding in functional decomposition, in: Proceedings of the 3rd International Workshop on Boolean Problems, Freiberg, Germany, 1998, pp. 19-29.
12. Chang S., Marek-Sadowska M., Hwang T. Technology mapping for tlu FPGAs based on decomposition of binary decision diagrams. IEEE Trans. CAD. 15(10):1996;1226-1236.
13. A. Chojnacki, L. Jóźwiak, Multi-valued sub-function encoding in functional decomposition based on information relationship measures, in: Proceedings of IEEE International Symposium on Multiple-Valued Logic, 2000, pp. 83-90.
14. Jóźwiak L. Simultaneous decomposition of sequential machines. Microprocess. Microprogram. 30:1990;305-312.
15. L. Jóźwiak, Decompositional logic synthesis: correctness aspects, in: Proceedings of APCHDLSA-93: Asian Pacific Conference on Hardware Description Languages, Standarts and Applications, Brisbane, Australia, 1993.
16. Jóźwiak L. General decomposition and its use in digital circuit synthesis. VLSI Design. 3(3):1995;225-248.
17. L. Jóźwiak, Information relationships and measures - an analysis apparatus for efficient information system synthesis, in: Proceedings of the 23rd EUROMICRO Conference, Budapest, Hungary, 1997, pp. 13-23.
18. L. Jóźwiak, Information relationship measures in application to logic design, in: Proceedings of IEEE International Symposium on Multiple-Valued Logic, Freiburg Im Breisgan, Germany, 1998.
19. L. Jóźwiak, A. Chojnacki, Effective and efficient FPGA synthesis through functional decomposition based on information relationship measures, in: Proceedings of DSD' - Euromicro Symposium on Digital System Design, 2001, pp. 30-37.
20. L. Jóźwiak, A. Chojnacki, High-quality sub-function construction in functional decomposition based on information relationship measures, in: Proceedings of . DATE' - Design, Automation, and Test in Europe Conference, Munich, Germany, 2001, pp. 383-390.
21. Jóźwiak L., Chojnacki A. Effective and efficient combinational circuit synthesis for the FPGA-based reconfigurable systems. Special Issue of Journal of Systems Architecture on Reconfigurable Computing. 49(4-6):2003;247-265.
22. Jóźwiak L., Kolsteren J. An efficient method for the sequential decomposition of sequential machines. Microprocess. Microprogram. 32:1991;657-664.
23. L. Jóźwiak, P. Konieczny, Input support minimization for efficient PLD and FPGA synthesis, in: Proceedings of International Workshop on Logic and Architecture Synthesis, 1996, pp. 30-32.
24. L. Jóźwiak, A. Ślusarczyk, A new state assignment method targeting FPGA implementations, in: Proceedings of EUROMICRO Symposium on Digital System Design DSD, Maastricht, the Netherlands, 2000, pp. 50-59.
25. L. Jóźwiak, A. Ślusarczyk, A. Chojnacki, Fast and compact sequential circuits through the information-driven circuit synthesis, in: Proceedings of DSD' - Euromicro Symposium on Digital System Design, Warsaw, Poland, 2001, pp. 46-53.
26. Jóźwiak L., Ślusarczyk A., Chojnacki A. Fast and compact sequential circuits for the FPGA-based reconfigurable systems. J. Syst. Architect. Reconfig. Comput. (Special Issue). 49(4-6):2003;227-246.
27. L. Jóźwiak, F. Vankan, Bit full decomposition of sequential machines: algorithms and results, in: Proceedings of the Canadian Conference on Electrical and Computer Engineering, Montreal, 1989.
28. L. Jóźwiak, F. Volf, An efficient method for decomposition of multiple output boolean functions and assigned sequential machines, in: Proceedings of EDAC - The European Conference on Design Automation, Brussels, Belgium, 1992, pp. 114-122.
29. Lai Y., Pan K., Pedram M. Obdd-based function decomposition: algorithms and implementation. IEEE Trans. CAD. 15(8):1996;977-990.
30. Luba T., Selvaraj H. A general approach to boolean function decomposition and its applications in FPGA-based synthesis. VLSI Design. (3-4):1995;289-300.
31. R. Malvi, M. Perkowski, L. Jóźwiak, Exact graph coloring for functional decomposition: do we need it, in: Proceedings of the 3rd International Workshop on Boolean Problems, Freiberg, Germany, 1998.
32. R. Murgai, R. Brayton, A.S. Vincentelli, Optimal functional decomposition using encoding, in: Proceedings of the 31st ACM/IEEE DAC, 1994, pp. 408-414.
33. R. Murgai, N. Shenoy, R. Brayton, A.S. Vincentelli, Performance directed synthesis for table look up programmable gate arrays, in: Proceedings of IEEE ICCAD, 1991, pp. 572-575.
34. M. Perkowski, M. Marek-Sadowska, L. Jóźwiak, T. Luba, S. Grygiel, M. Nowicka., R. Malvi., Z. Wang, S. Zhang, Decomposition of multiple-valued relations, in: Proceedings of International Symposium on Multiple-Valued Logic, 1997, pp. 13-18.
35. Rawski M., Jóźwiak L., Luba T. Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. J. Syst. Architect. 2(47):2001;137-155.
36. M. Rawski, L. Jóźwiak, M. Nowicka, T. Luba, Non-disjoint decomposition of boolean functions and its application in FPGA-oriented technology mapping, in: Proc. of the EUROMICRO'97 Conference, Budapest, Hungary, 1997, pp. 24-30.
37. W.-Z. Shen, J.-D. Huang, S.-M. Chao, Lambda set selection in roth-karp decomposition for LUT-based FPGA technology mapping, in: Proceedings of the 32nd ACM/IEEE Design Automation Conference, 1995.
38. C. Sholl, P. Molitor, Communication-based FPGA synthesis for multi-output boolean functions, in: Proceedings of the Asia and South Pacific Design Automation Conference, Chiba, Japan, 1995, pp. 279-288.
39. F. Volf, L. Jóźwiak, Decompositional logic synthesis approach for look up table based FPGAs, in: Proceedings of the 8th IEEE International ASIC Conference, Austin, Texas, 1995.
40. Volf F., Jóźwiak L., Stevens M. Division-based versus general decomposition-based multiple-level logic synthesis. VLSI Design. 3(3):1995;267-287.
41. L. Jóźwiak, S. Biegański, Information-driven library-based circuit synthesis, in: Proceedings of the Euromicro Symposium on Digital Systems Design, 2003, pp. 148-155.
42. V. Bertacco, M. Damiani, The disjunctive decomposition of logic functions, in: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1997, pp. 78-82.
43. S. Minato, G. De Micheli, Finding all simple disjunctive decompositions using irredundant sum-of-products forms, in: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 111-117.
44. T. Stanion, C. Sechen, A method for finding good Ashenhurst decomposition and its application to FPGA synthesis, in: Proceedings of the ACM/IEEE Design Automation Conference, San Francisco, CA, 1995, pp. 60-64.
45. S. Yamashita, H. Sawada, A. Nagoya, New methods to find optimal non-disjoint bi-decomposition, in: Proceedings of Design Automation Conference, 1998, pp. 59-68.
46. Yang C., Ciesielski M. Bds: a bdd-based logic optimization system. Trans. Comput.-Aided Design of Integrat. Syst. Circuits. 21:2002;866-876.
47. Sawada H., Suyama T., Nagoya A. Logic synthesis for look-up table based FPGAs using functional decomposition and Boolean resubstitution. IEICE Trans. Inform. Syst. E80-D(10):1997;1017-1023.
48. Sasao T. Logic Synthesis for VLSI Design. 1993;Kluwer Academic Publishers, Dordrecht. (Chapter: FPGA design by generalized functional decomposition).
49. Fujita M., Mastunaga Y., Ciesielski M. Logic Synthesis and Verification. 2002;Kluwer Academic Publishers, Dordrecht. (Chapter: Multi-level logic optimization).
50. Shannon C.E. The synthesis of two-terminal switching circuits. Bell Syst. Techn. J. 28:1949;59-98.
51. Povarov G.H. On functional separation of Boolean functions. Lectures of the USSR Acad. Sci. 95(5):1954;801-803. (in Russian).
52. R. Ashenhurst, The decomposition of switching functions, in: Proceedings of International Symposium on the Theory of Switching Functions, 1959, pp. 74-116.
53. J. Roth, R. Karp, Minimization over boolean graphs, IBM J. Res. Dev., April (1962).
54. Curtis H.A. A generalized tree circuits. J. Assoc. Comput. Mach. 8:1961;484-496.
55. Hartmanis J., Stearns R. Algebraic Structure Theory of Sequential Machines. 1966;Prentice-Hall, Englewood Cliffs, NJ.
56. Hartmanis J. Symbolic analysis of a decomposition of information processing. Inform. Contr. 5:1960;154-178.
57. Hartmanis J. Loop-free structure of sequential machines. Inform. Contr. 5:1962;25-43.
58. S.-C. Chang, M. Marek-Sadowska, Technology mapping via transformations of function graphs, in: Proceedings of the IEEE International Conference on Computer Design, Cambridge, MA, 1992, pp. 159-162.
59. Y.T. Lai, M. Pedram, S. Vrudhula, BDD-based decomposition of logic functions with application to FPGA synthesis, in: ACM/IEEE Design Automation Conference, 1993, pp. 642-647.
60. Legl C., Wurth B., Eckl K. Computing support-minimal subfunctions during functional decomposition. IEEE Trans. Very Large Scale Integrat. [VLSI] Syst. 6(3):1998;354-363.
61. Wurth B., Schlichtmann U., Eckl K., Antreich K. Functional multiple-output decomposition with application to technology mapping for look-up table based FPGAs. ACM Trans. Design Autom. Electron. Syst. 4(3):1999.
62. K. Eckl, C. Legl, B. Wurth, An implicit approach to functional decomposition of incompletely specified boolean functions, in: Proceedings of the International Workshop on Logic and Synthesis IWLS'97, 1997.
63. H. Sawada, T. Suyama, A. Nagoya, Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization, in: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1995, pp. 355-358.
64. Möhring R.H. Algorithmic aspects of the substitution decomposition in optimization over relations, set systems and boolean functions. Ann. Operat. Res. 4:1985;195-225.
65. T. Luba, et al., Combining serial decomposition with topological partitioning for effective multi-level PLA implementations, in: Proceedings of IFIP Working Conference on Logic and Architecture Synthesis, 1990, pp. 77-86.
66. M. Rawski, L. Jóźwiak, T. Lłuba, The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition, in: Proceedings of the 25th EUROMICRO Conference, 1999, Milan, Italy.
67. L. Jóźwiak, N. Ederveen, Genetic algorithm for input support minimization, in: Proceedings of the International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'98), Melbourne, Australia, 1998.