Multi-output functional decomposition with exploitation of don't cares

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 743-748

  Scholl, Christoph ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DECOMPOSITION; DECOMPOSITION ALGORITHM; FPGA ARCHITECTURES; FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS; MULTI-OUTPUT; NOVEL CONCEPT; SUBFUNCTIONS;

ALGORITHMS; BOOLEAN FUNCTIONS;

LOGIC DESIGN;

EID: 0011835042     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655941     Document Type: Conference Paper

References (25)

1. R.L. Ashenhurst. The decomposition of switching functions. In Int'l Symp. on Theory Switching Funct., pages 74-116, 1959.
2. S. Chang, D. Cheng, and M. Marek-Sadowska. Minimizing ROBDD size of incompletely specified multiple output functions. In European Design &Test Conf., pages 620-624, 1994.
3. S.-C. Chang and M. Marek-Sadowska. BDD representation of incompletely specified functions. In Int'l Workshop on Logic Synth., pages P6c:1-6, 1993.
4. H.A. Curtis. A generalized tree circuit. Journal of the ACM, 8:484-496, 1961.
5. K. Eckl, C. Legl, and B. Wurth. An implicit approach to functional decomposition of incompletely specified boolean functions. In Int'l Workshop on Logic Synth., 1997.
6. C.R. Edwards and S.L. Hurst. A digital synthesis procedure under function symmetries and mapping methods. IEEE Trans. on Comp., 27:985-997, 1978.
7. G. Hotz. Schaltkreistheorie. Walter de Gruyter, 1974.
8. R.M. Karp. Functional decomposition and switching circuit design. J. Soc. Indust. Appl. Math., 11(2):291-335, 1963.
9. Y.-T. Lai, K.-R. Pan, M. Pedram, and S. Sastry. FGMap: A technology mapping algorithm for look-up table type FPGAs based on function graphs. In Int'l Workshop on Logic Synth., pages 9b1-9b4, 1993.
10. Y.-T. Lai, M. Pedram, and S.B.K. Vrudhula. BDD based decomposition of logic functions with application to FPGA synthesis. In Design Automation Conf., pages 642-647, 1993.
11. Y.-T. Lai, M. Pedram, and S.B.K. Vrudhula. EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans. on CAD, 13(8), 1994.
12. P. Molitor and C. Scholl. Communication Based Multilevel Synthesis for Multi-Output Boolean Functions. In Great Lakes Symp. VLSI, pages 101-104, 1994.
13. D. Moller, P. Molitor, and R. Drechsler. Symmetry based variable ordering for ROBDDs. IFIP Workshop on Logic and Architecture Synthesis, Grenoble, pages 47-53, 1994.
14. R. Murgai, Y. Nishizaki, N. Shenoy, R.K. Brayton, and A. Sangiovanni-Vincentelli. Logic synthesis for programmable gate arrays. In Design Automation Conf., pages 620-625, 1990.
15. R. Murgai, N. Shenoy, R.K. Brayton, and A. Sangiovanni-Vincentelli. Improved logic synthesis algorithms for table look up architectures. In Int'l Conf. on CAD, pages 564-567, 1991. Number of CLBs Circuit mulop-dcII4 FGMap mis-pga(new)
16. S. Panda, F. Somenzi, and B.F. Plessier. Symmetry detection and dynamic variable ordering of decision diagrams. In Int'l Conf. on CAD, pages 628-631, 1994.
17. J.P. Roth and R.M. Karp. Minimization over Boolean graphs. IBM J. Res. and Develop., 6(2):227-238, 1962.
18. A. Sangiovanni-Vincentelli, A.E. Gamal, and J. Rose. Synthesis methods for field programmable gate arrays. Proc. of the IEEE, 81:1057-1083, 1993.
19. T. Sasao. Logic Synthesis and Optimization. Kluwer Academic Publisher, 1993.
20. C. Scholl. Mehrstufige Logiksynthese unter Ausnutzung funktionaler Eigenschaften. PhD thesis, Universitat des Saarlandes, 1996.
21. C. Scholl, S. Melchior, G. Hotz, and P. Molitor. Minimizing ROBDD sizes of incompletely specified functions by exploiting strong symmetries. In European Design &Test Conf., pages 229-234, 1997.
22. C. Scholl and P. Molitor. Communication based FPGA synthesis for multi-output Boolean functions. In ASP Design Automation Conf., pages 279-287, 1995.
23. J. Slansky. Conditional-sum addition logic. IEEE Trans. on Electronic Comp., 9:226-231, 1960.
24. C.S. Wallace. A suggestion for a fast multiplier. IEEE Trans. on Comp., 13:14-17, 1964.
25. B. Wurth, K. Eckl, and K. Antreich. Functional multiple-output decomposition: Theory and implicit algorithm. In Design Automation Conf., pages 54-59, 1995.