-
1
-
-
0025536718
-
Logic synthesis for programmable gate arrays
-
June
-
R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Logic synthesis for programmable gate arrays," in Proc. 27th ACM/IEEE Design Automation Conf., DAC, June 1990, pp. 620-625.
-
(1990)
Proc. 27th ACM/IEEE Design Automation Conf., DAC
, pp. 620-625
-
-
Murgai, R.1
Nishizaki, Y.2
Shenoy, N.3
Brayton, R.K.4
Sangiovanni-Vincentelli, A.L.5
-
2
-
-
0028561315
-
Optimum functional decomposition using encoding
-
R. Murgai, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Optimum functional decomposition using encoding," in Proc. 31st ACM/IEEE Design Automation Conf., DAC, 1994, pp. 408-414.
-
(1994)
Proc. 31st ACM/IEEE Design Automation Conf., DAC
, pp. 408-414
-
-
Murgai, R.1
Brayton, R.K.2
Sangiovanni-Vincentelli, A.3
-
3
-
-
0027271156
-
BDD based decomposition of logic functions with application to FPGA synthesis
-
June
-
Y.-T. Lai, M. Pedram, and S. Vrudhula, "BDD based decomposition of logic functions with application to FPGA synthesis," in Proc. 30st ACM/IEEE Design Automation Conf., DAC, June 1993, pp. 642-647.
-
(1993)
Proc. 30st ACM/IEEE Design Automation Conf., DAC
, pp. 642-647
-
-
Lai, Y.-T.1
Pedram, M.2
Vrudhula, S.3
-
6
-
-
0028518320
-
Logic synthesis for field-programmable gate arrays
-
Oct.
-
T.-T. Hwang, R. M. Owens, M. J. Irwin, and K. H. Wang, "Logic synthesis for field-programmable gate arrays," IEEE Trans. Computer-Aided Design, vol. 13, Oct. 1994.
-
(1994)
IEEE Trans. Computer-Aided Design
, vol.13
-
-
Hwang, T.-T.1
Owens, R.M.2
Irwin, M.J.3
Wang, K.H.4
-
7
-
-
0029215231
-
Functional multiple-output decomposition: Theory and an implicit algorithm
-
B. Wurth, K. Eckl, and K. Antreich, "Functional multiple-output decomposition: Theory and an implicit algorithm," in Proc. 32nd ACM/IEEE Design Automation Conf., DAC, 1995, pp. 54-59.
-
(1995)
Proc. 32nd ACM/IEEE Design Automation Conf., DAC
, pp. 54-59
-
-
Wurth, B.1
Eckl, K.2
Antreich, K.3
-
8
-
-
0029216317
-
A method for finding good Ashenhurst decompositions and its application to FPGA synthesis
-
T. Stanion and C. Sechen, "A method for finding good Ashenhurst decompositions and its application to FPGA synthesis," in Proc. 32nd ACM/IEEE Design Automation Conf, DAC, 1995, pp. 60-64.
-
(1995)
Proc. 32nd ACM/IEEE Design Automation Conf, DAC
, pp. 60-64
-
-
Stanion, T.1
Sechen, C.2
-
9
-
-
0029227125
-
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
-
W. Z. Shen, J.-D. Huang, and S.-M. Chao, "Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping," in Proc. 32nd ACM/IEEE Design Automation Conf., DAC, 1995, pp. 65-69.
-
(1995)
Proc. 32nd ACM/IEEE Design Automation Conf., DAC
, pp. 65-69
-
-
Shen, W.Z.1
Huang, J.-D.2
Chao, S.-M.3
-
10
-
-
0029513452
-
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
-
Nov.
-
J.-D. Huang, J.-Y. Jou, and W.-Z. Shen, "Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design ICCAD, Nov. 1995, pp. 359-363.
-
(1995)
Proc. IEEE/ACM Int. Conf. Computer-Aided Design ICCAD
, pp. 359-363
-
-
Huang, J.-D.1
Jou, J.-Y.2
Shen, W.-Z.3
-
11
-
-
0030674145
-
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping
-
Feb.
-
J. Cong and Y.-Y. Hwang, "Partially-dependent functional decomposition with applications in FPGA synthesis and mapping," in Fifth Int. Symp. Field-Programmable Gate Arrays, Feb. 1997.
-
(1997)
Fifth Int. Symp. Field-Programmable Gate Arrays
-
-
Cong, J.1
Hwang, Y.-Y.2
-
12
-
-
0030214752
-
OBDD - Based function decomposition: Algorithms and implementation
-
Aug.
-
Y.-T. Lai, K.-R. R. Pan, and M. Pedram, "OBDD - Based function decomposition: Algorithms and implementation," IEEE Trans. Computer-Aided Design, vol. 15, pp. 977-990, Aug. 1996.
-
(1996)
IEEE Trans. Computer-Aided Design
, vol.15
, pp. 977-990
-
-
Lai, Y.-T.1
Pan, K.-R.R.2
Pedram, M.3
-
13
-
-
0000568889
-
Minimization over Boolean graphs
-
J. P. Roth and R. M. Karp, "Minimization over Boolean graphs," IBM J., pp. 227-238, 1962.
-
(1962)
IBM J.
, pp. 227-238
-
-
Roth, J.P.1
Karp, R.M.2
-
15
-
-
33747786652
-
Functional multiple-output decomposition for lookup-table based FPGA's
-
CA, May
-
B. Wurth, K. Eckl, and K. Antreich, "Functional multiple-output decomposition for lookup-table based FPGA's," in Proc. Workshop Notes Int. Workshop Logic Synth. IWLS, CA, May 1995, pp. 9-26-9-37.
-
(1995)
Proc. Workshop Notes Int. Workshop Logic Synth. IWLS
, pp. 926-937
-
-
Wurth, B.1
Eckl, K.2
Antreich, K.3
-
16
-
-
0029779087
-
An implicit algorithm for support minimization during functional decomposition
-
Mar.
-
C. Legl, B. Wurth, and K. Eckl, "An implicit algorithm for support minimization during functional decomposition," in Proc. European Design Test Conf. ED&TC, Mar. 1996, pp. 412-417.
-
(1996)
Proc. European Design Test Conf. ED&TC
, pp. 412-417
-
-
Legl, C.1
Wurth, B.2
Eckl, K.3
-
17
-
-
0028554370
-
A fully implicit algorithm for exact state minimization
-
T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli, "A fully implicit algorithm for exact state minimization," in Proc. 31st ACM/IEEE Design Automation Conf. DAC, 1994, pp. 684-690.
-
(1994)
Proc. 31st ACM/IEEE Design Automation Conf. DAC
, pp. 684-690
-
-
Kam, T.1
Villa, T.2
Brayton, R.3
Sangiovanni-Vincentelli, A.4
-
18
-
-
0029708450
-
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
-
June
-
C. Legl, B. Wurth, and K. Eckl, "A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs," in Proc. 33rd ACM/IEEE Design Automation Conf., DAC, June 1996, pp. 730-733.
-
(1996)
Proc. 33rd ACM/IEEE Design Automation Conf., DAC
, pp. 730-733
-
-
Legl, C.1
Wurth, B.2
Eckl, K.3
-
20
-
-
0028341924
-
Routability-driven technology mapping for lookup table-based FPGA's
-
Jan.
-
M. Schlag, J. Kong, and P. K. Chan, "Routability-driven technology mapping for lookup table-based FPGA's," IEEE Trans. Computer-Aided Design, vol. 13, pp. 13-26, Jan. 1994.
-
(1994)
IEEE Trans. Computer-Aided Design
, vol.13
, pp. 13-26
-
-
Schlag, M.1
Kong, J.2
Chan, P.K.3
-
21
-
-
25544475739
-
FGMap: A technology mapping algorithm for look-up table type FPGA's based on function graphs
-
May
-
Y.-T. Lai, K.-R. R. Pan, M. Pedram, and S. Sastry, "FGMap: A technology mapping algorithm for look-up table type FPGA's based on function graphs," in Proc. Workshop Notes Int. Workshop Logic Synth. IWLS, May 1993, pp. 9b1-9b4.
-
(1993)
Proc. Workshop Notes Int. Workshop Logic Synth. IWLS
-
-
Lai, Y.-T.1
Pan, K.-R.R.2
Pedram, M.3
Sastry, S.4
-
22
-
-
0003934798
-
-
Electron. Res. Lab., Memo. UCB/ERL M92/41, May
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis," Electron. Res. Lab., Memo. UCB/ERL M92/41, pp. 1-45, May 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
, pp. 1-45
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni-Vincentelli, A.10
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