Logic synthesis for look-up table based fpgas using functional decomposition and boolean resubstitution

IEICE Transactions on Information and Systems

Volumn E80-D, Issue 10, 1997, Pages 1017-1023

  Sawada, Hiroshi ^a   Suyama, Takayuki ^a   Nagoya, Akira ^a  

^a NTT Communication Science Laboratories   (Japan)

Author keywords

Boolean resubstitution; FPGA; Functional decomposition; Look up table (LUT); Support minimization

Indexed keywords

BOOLEAN FUNCTIONS; FUNCTION EVALUATION; LOGIC GATES; TABLE LOOKUP;

BOOLEAN RESUBSTITUTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS; SUPPORT MINIMIZATION;

LOGIC DESIGN;

EID: 0031251335     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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