Prediction of Interconnect Pattern Density Distribution: Derivation, Validation, and Applications

International Workshop on System Level Interconnect Prediction

Volumn , Issue , 2003, Pages 85-91

  Zarkesh Ha, Payman ^a   Doniger, Ken ^a   Loh, William ^a   Wright, Peter ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

Interconnect network prediction; Interconnect pattern density; Probability density function; Stochastic model

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; LOGIC DESIGN; MONTE CARLO METHODS; PARAMETER ESTIMATION; PROBABILITY DENSITY FUNCTION; PROBABILITY DISTRIBUTIONS; RANDOM PROCESSES; SAMPLING;

INTERCONNECT NETWORK PREDICTION; INTERCONNECT PATTERN DENSITY;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 1442278926     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. S. Nassif, "Design for variability in DSM technologies," Proceedings of IEEE ISQED, pp. 451-454, March 2000.
2. S. Nassif, "Within-chip variability analysis," Proceedings of IEDM, pp. 283-286, Dec. 1998.
3. V. Mehrotra, S. Sam, D. Boning, A. Chandrakanan, R. Vallishayee, and S. Nassif, "A methodology for modeling the effects of systematic process variations on circuit performance," Proceedings of DAC, pp. 172-175, June. 2000.
4. V. Mehrotra, S. Nassif, D. Boning, and J. Chung, "Modeling the effects of manufacturing variations on high-speed microprocessor interconnect performance," Proceedings of IEDM, pp. 767-770, Dec. 1998.
5. P. Zarkesh-Ha, S. Lakshminarayann, K. Doniger, W. Loh, and P. Wright, "Impact of interconnect pattern density information on a 90nm technology ASIC design flow," will appear in the proceedings of IEEE ISQED, March 2003.
6. J. A. Davis, V. K. De and J. D. Meindl, "A stochastic wirelength distribution for gigascale integration (GSI): Part I: Derivation and validation," IEEE Transaction on Electron Devices, Vol. 45, No. 3, pp. 580-589, March 1998.
7. P. Christie, J. P. Gyvez, "Pre-layout prediction of interconnect manufacturability", Proceedings of SLIP, pp. 167-173, April 2001.
8. V. Sukharev, P. Zarkesh-Ha, C.H. Chang, and W. Loh, "Metal density optimization with CMP-based dummy placement," Proceedings of the CMP-MIC Conference, pp. 453-462, February 2003.
9. S. Lakshminarayanan, P. Wright, and Jayanthi Pallinti, "Design rule methodology to improve the manufacturability of the copper CMP process," Proceedings of the IEEE IITC, pp. 99-101, June 2002.
10. T. Shih, C.H. Yao, L.K. Huang, S.M. Jang, C.H. Yu, and M.S. Liang, "Pattern dependence study of copper planarization using linear polisher for 0.13 μm applications," Proceedings of IEEE IITC, pp. 51-53, June 2001.