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Volumn 5, Issue , 2003, Pages

Voltage scaling and repeater insertion for high-throughput low-power interconnects

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; POWER SUPPLY CIRCUITS; TELECOMMUNICATION REPEATERS; THROUGHPUT;

EID: 0038758724     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (12)

References (8)
  • 1
    • 0038111466 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors (http://public.itrs.net)
  • 3
    • 0033741257 scopus 로고    scopus 로고
    • Investigation on maximal throughput of a CMOS repeater chain
    • Apr
    • Per Larsson-Edefors, "Investigation on Maximal Throughput of a CMOS Repeater Chain," IEEE Transactions on Circuits and Systems-I, Vol.47, No.4, pp.602-606, Apr 2000.
    • (2000) IEEE Transactions on Circuits and Systems-I , vol.47 , Issue.4 , pp. 602-606
    • Larsson-Edefors, P.1
  • 4
    • 0036907334 scopus 로고    scopus 로고
    • Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
    • Harshit Shah and Jeffrey Davis, "Repeater Insertion and Wire Sizing Optimization for Throughput-Centric VLSI Global Interconnects," ICCAD, 2002.
    • (2002) ICCAD
    • Shah, H.1    Davis, J.2
  • 6
    • 0038450785 scopus 로고    scopus 로고
    • for HSPICE models
    • The MOSIS Service (http://www.mosis.org) for HSPICE models.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.