Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 434-441

  Fournier, Laurent ^a   Arbetman, Yaron ^a   Levinger, Moshe ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING POINTS; FUNCTIONAL VERIFICATION; MICROPROCESSOR DESIGNS; PENTIUM; PSEUDO RANDOM; RIGOROUS METHODOLOGIES; VERIFICATION PLANS; VERIFICATION TASK;

DESIGN; EXHIBITIONS;

MICROPROCESSOR CHIPS;

EID: 0001909165     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761162     Document Type: Conference Paper

References (10)

1. Y. Lichtenstein, Y. Malka and A. Aharon, "Model-Based Test Generation For Processor Design Verification", Innovative Applications of Artificial Intelligence (IAAI), AAAI Press, 1994.
2. H.P. Sharangpani, M.L. Barton, "Statistical Analysis of Floating Point Flaw in the Pentium Processor", Intel Corporation, 1994.
3. F. Casaubieilh et al., "Functional Verification Methodology of Chameleon Processor", 33rd Design Automation Conference, Las Vegas, June 1996, pp. 421-426.
4. A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek, "Test Program Generation for Functional Verification of PowerPC Processors in IBM", 32nd Design Automation Conference, San Francisco, June 1995, pp. 279-285.
5. A. L. Sangiovanni-Vincentelli, P. C. McGeer, A. Saldanha, "Verification of Electronic Systems", 33rd Design Automation Conference, pp. 106-111.
6. J. Monaco, D. Holloway, R. Raina, "Functional Verification Methodology for the PowerPC 604 Microprocessor", 33rd. Design Automation Conference, pp. 319-324.
7. M. Kantrowitz, L. M. Noack, "I'm Done Simulating; Now What?", 33rd Design Automation Conference, pp. 325-330.
8. D. Lewin, L. Fournier, M. Levinger, E. Roytman, G. Shurek, "Constraint Satisfaction for Test Program Generation", IEEE 14th Phoenix Conference on Computers and Communications, 1995.
9. Intel Pentium II flag erratum, Intel home page at: http:// developer.intel.com/design/news/flag/tech.htm
10. G. Ganapathy, R. Narayan, G. Jorden, D. Fernandez, "Hardware Emulation for Functional Verification of K5", 33rd Design Automation Conference, pp. 315-318.