Generating concurrent test-programs with collisions for multi-processor verification

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2002-January, Issue , 2002, Pages 77-82

  Adir, A ^a   Shurek, G ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

Automatic testing; Gas insulated transmission lines; Laboratories; Out of order; Performance evaluation; Predictive models; Programming profession; Registers; Switches; Yarn

Indexed keywords

AUTOMATIC TESTING; LABORATORIES; MULTIPROCESSING SYSTEMS; SWITCHES; TESTBEDS; YARN;

GAS INSULATED TRANSMISSION LINES; OUT OF ORDER; PERFORMANCE EVALUATION; PREDICTIVE MODELS; PROGRAMMING PROFESSION; REGISTERS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84949213246     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2002.1224432     Document Type: Conference Paper

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