Improving test quality through resource reallocation

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 64-69

  Adir, A ^a   Marcus, E ^a   Rimon, M ^a   Voskoboynik, A ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

TESTING;

CODE-PATTERNS; RESOURCE REALLOCATION; RESOURCE VALUE; TEST PROGRAM; TEST QUALITY;

SOFTWARE TESTING;

EID: 1442316898     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972809     Document Type: Conference Paper

References (8)

1. A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of PowerPC processors in IBM. In the 32nd Design Automation Conference, pages 279-285, 1995.
2. A. M. Ahi, G. D. Burroughs, A. B. Gore, S. W. LaMar, C. R. Lin, and A. L. Wiemann. Design verification of the HP 9000 series 700 PA-RISC workstations. Hewlett-Packard Journal, 14(8), August 1992.
3. L. Fournier, Y. Arbetman, and M. Levinger. Functional verification methodology for microprocessors using the Genesys test program generator - application to the x86 microprocessors family. In DATE99, Munchen, pages 434-441, 1999.
4. D. Geist, G. Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, K. Holtz, A. Long, D. King, and S. Barret. A methodology for the verification of a "system on a chip". In the 36th Design Automation Conference, pages 574-579, 1999.
5. A. Hartman, S. Ur, and A. Ziv. Short vs long: Size does make a difference. In HLDVT, 1999.
6. A. Hosseini, D. Mavroidis, and P. Konas. Code generation and analysis for the functional verification of microprocessors. In the 33rd Design Automation Conference, pages 305-310, 1996.
7. S. Taylor, M. Quinn, D. Brown, N. Dohm, S. Hildebrandt, J. Huggins, and C. Ramey. Functional verification of a multiple-issue, out-of-order, superscalar alpha processor - the DEC Alpha 21264 microprocessor. In the 35th Design Automation Conference, pages 638-643, 1998.
8. A. Ziv and L. Fournier. Test generation for the binary floating point add operation with mask-mask-mask constraints. To appear in special issue "Real Numbers and Computers" of the "Theoretical Computer Science" journal.