Microstructural characterization of inlaid copper interconnect lines

Journal of Electronic Materials

Volumn 30, Issue 4, 2001, Pages 320-330

  Besser, Paul R ^a   Zschech, Ehrenfried ^b   Blum, Werner ^b   Winter, Delrose ^c   Ortega, Richard ^c   Rose, Stewart ^d   Herrick, Matt ^d   Gall, Martin ^d   Thrasher, Stacye ^d   Tiner, Mike ^d   Baker, Brett ^d   Braeckelmann, Greg ^b,d   Zhao, Larry ^a   Simpson, Cindy ^d   Capasso, Cristiano ^d   Kawasaki, Hisao ^d   Weitzman, Elizabeth ^d  

^a ADVANCED MICRO DEVICES   (United States)

^b Adv Micro Devices Saxony Mfg GmbH   (Germany)

^c AMIA Laboratories Rigaku   (United States)

^d MOTOROLA INC   (United States)

Author keywords

Copper; Grain size; Interconnects; Microstructure; Stress; Texture

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; COPPER; CRYSTAL MICROSTRUCTURE; CRYSTAL ORIENTATION; GRAIN SIZE AND SHAPE; NUCLEATION; SILICA; TENSILE STRESS; TEXTURES; VLSI CIRCUITS; X RAY DIFFRACTION ANALYSIS;

CRYSTALLOGRAPHIC TEXTURES; INLAID COPPER INTERCONNECT LINES; INTERLAYER DIELECTRICS;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 18544402220     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-001-0038-7     Document Type: Article

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