Feed forward test methodology utilizing device identification

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 655-660

  Cabbibo, A ^a   Conder, J ^a   Jacobs, M ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA SOURCES; LIMIT SETTING; TEST PROGRAMS; WAFER TABLES;

COSTS; CUSTOMER SATISFACTION; DATA ACQUISITION; DATABASE SYSTEMS; EQUIPMENT TESTING; MICROPROCESSOR CHIPS; PROM; SEMICONDUCTOR DEVICE MANUFACTURE;

INTEGRATED CIRCUIT TESTING;

EID: 18144373139     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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4. R. Miller, W. Riordan, "Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort" ITC International Test Conference, 2001.
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7. W.R. Daasch, J. McNames, D. Bockelman, K. Cota, R. Madge, "Variance Reduction using Wafer patterns in IDDQ Data," ITC International Test Conference, 2000.
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10. R. Daasch, et al., "Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data," Int. Test Conf., pp. 1240-1248, 2002.