Power comparison of throughput optimized IC busses

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 35-44

  Malley, E ^a   Salinas, A ^a   Ismail, K ^a   Pileggi, L ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Clocks; Communication channels; Delay effects; Design methodology; Fabrication; Microprocessors; Power distribution; Throughput; Timing; Wire

Indexed keywords

BUSES; CLOCKS; COMMUNICATION CHANNELS (INFORMATION THEORY); DESIGN; DIGITAL STORAGE; FABRICATION; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; PULSE GENERATORS; SYSTEM BUSES; THROUGHPUT; WIRE;

DELAY EFFECTS; DESIGN METHODOLOGY; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; POWER DISTRIBUTIONS; SWITCHING ACTIVITIES; SYNCHRONOUS CONTROL; THROUGHPUT-OPTIMIZED; TIMING;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84942044477     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183351     Document Type: Conference Paper

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