A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 372-377

  Rapaka, V S P ^a   Marculescu, D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Circuit synthesis; Clocks; Concrete; Distributed computing; Energy consumption; Microprocessors; Out of order; Signal design; Synchronous generators; Transistors

Indexed keywords

CLOCKS; CONCRETES; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; ENERGY UTILIZATION; INTEGRATED CIRCUIT MANUFACTURE; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; QUEUEING THEORY; SYNCHRONOUS GENERATORS; TRANSISTORS;

ARCHITECTURAL EVALUATION; CIRCUIT DESIGN TECHNIQUES; CIRCUIT SYNTHESIS; COMPUTATIONAL CAPABILITY; GLOBALLY ASYNCHRONOUS , LOCALLY SYNCHRONOUS; OUT OF ORDER; OUT-OF-ORDER PROCESSORS; SIGNAL DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 1542299265     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231926     Document Type: Conference Paper

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