Transistor and pin reordering for gate oxide leakage reduction in dual T ox circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 228-233

  Sultania, Anup Kumar ^a   Sylvester, Dennis ^b   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE OXIDE LEAKAGE CURRENTS; GATE OXIDE TUNNELING CURRENTS; POWER DISSIPATION; SUBTHRESHOLD LEAKAGE;

CMOS INTEGRATED CIRCUITS; ELECTRIC FIELDS; ELECTRON TUNNELING; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; SWITCHING; THRESHOLD VOLTAGE;

GATES (TRANSISTOR);

EID: 17644368287     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347927     Document Type: Conference Paper

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