Data retention time in DRAM with WSix/P+ poly-Si gate NMOS cell transistors

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 395-398

  Kujirai, Hiroshi ^a   Ohyu, Kiyonori ^a   Moniwa, Masahiro ^a   Kato, Hideaki ^a   Nakai, Kiyoshi ^a   Iwai, Hidetoshi ^a   Nanba, Mitsuo ^a   Ogishima, Atsushi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); MOSFET DEVICES; PROBABILITY DISTRIBUTIONS; SEMICONDUCTING SILICON; SEMICONDUCTOR STORAGE; TIME SERIES ANALYSIS;

CELL TRANSISTORS; CHANNEL DOPING LEVEL; DATA RETENTION TIME;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035718111     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling
2. Low voltage circuit design techniques for battery-operated and/or giga-scale DRAM's
3. Dual (n+/p+) polycide interconnect technology using poly-Si/WSi2/poly-Si structure and post B+ implantation
4. Buried ultra-low-energy gate implants for sub-0.25micron CMOS technology
5. Local-field-enhancement model of DRAM retention failure
6. A new model for the description of gate voltage and temperature dependence of gate induced drain leakage (GIDL) in the low electric field region
7. Numerical analysis of an anomalous current assisted by locally generated deep traps in pn junctions
8. A strategy for long data retention time of 512Mb DRAM with 0.12um design rule