A new method for predicting distribution of DRAM retention time

IEEE International Reliability Physics Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 7-11

  Mori, Y ^a   Yamada, R I ^a   Kamohara, S ^a   Moniwa, M ^a   Ohyu, K ^a   Yamanaka, O ^a  

^a HITACHI LTD   (Japan)

Author keywords

Circuit testing; Current measurement; DRAM chips; Equivalent circuits; Leakage current; MOSFET circuits; Predictive models; Probability distribution; Random access memory; Tail

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; EQUIVALENT CIRCUITS; LEAKAGE CURRENTS; PROBABILITY DISTRIBUTIONS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

CIRCUIT TESTING; DRAM CHIPS; MOSFET CIRCUITS; PREDICTIVE MODELS; RANDOM ACCESS MEMORY; TAIL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84949799252     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2001.922873     Document Type: Conference Paper

References (3)

1. C. M. Nam et al., "A New Extraction Method of Retention Time from the Leakage Current in 0.23μm DRAM Memory Cellin," ICMTS Proc., 2000, p102
2. S. Ueno et al., "Leakage Current Observation on Irregular Local PN Junctions Forming the Tail Distribution of DRAM Retention Characteristics, with New Test Structure," in IEDM Tech. Dig., 1998, p153
3. S. Kamohara et al., "Statistical PN Junction Leakage Model with Trap level Fluctuation for Tref (Refresh Time) - Oriented DRAM Design," in IEDM Tech. Dig., 1999, p539