Boolean process

Science in China, Series E: Technological Sciences

Volumn 40, Issue 3, 1997, Pages 250-257

  Min, Yinghua ^a   Li, Zhongcheng ^a   Zhao, Zhuxing ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

Boolean process; Path sensitization; Waveform; Waveform limit

Indexed keywords

EID: 0343205869     PISSN: 10069321     EISSN: None     Source Type: Journal    
DOI: 10.1007/bf02916600     Document Type: Article

References (7)

1. Moszkowski, B., A temporal logic for multilevel reasoning about hardware, Computer, 1985, 18(2): 10.
2. Am Ward, P., Caspi, P., Halbwachs, N., Use of time functions to describe and explain circuit behavior, IEE Proceedings, Pt.E, 1986, 122(5), 271.
3. Min, Y., Boolean process - An analytical approach to circuit representation, in Proc. IEEE Third Asian Test Symposium, Nara, Japan, Bangalore: IEEE Computer Society Press, 1994, 249-254.
4. Min,Y., Zhao, Z., Li, Z., Boolean process - An analytical approach to circuit representation (II), in Proc. IEEE Fourth Asian Test Symposium, India, Bangalore: IEEE Computer Society Press, 1995, 26-32.
5. Min, Y., Zhao, Z., Li, Z., Analytical delay models for delay testing, in Proc. VLSI Design Conf. 96, India, Bangalore: IEEE Computer Society Press, 1996.
6. Lam, K. C., Brayton, R. K., Timed Boolean Functions, Boston: Kluwer Academic Publishers, 1994, 273.
7. McCluskey, E. J., Transients in combinational logic circuits, in Redundancy Techniques for Computing Systems, Washington, D. C. : Spartan Book, 1962, 9-46.