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Volumn 18, Issue 1, 2002, Pages 17-28

Test generation for crosstalk-induced faults: Framework and computational results

Author keywords

Crosstalk; Fault modeling; Mixed signal test; Time based test generation

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CROSSTALK; DIGITAL INTEGRATED CIRCUITS; ERRORS; VECTORS;

EID: 0036471001     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1013771821826     Document Type: Article
Times cited : (19)

References (24)
  • 8
    • 26344469664 scopus 로고    scopus 로고
    • Timing analysis for test generation for crosstalk-induced delay in integrated circuits
    • Computer Engineering Technical Report No. 99-04, Electrical Engineering-Systems Department, University of Southern California, April
    • (1999)
    • Chen, W.Y.1    Breuer, M.A.2    Gupta, S.K.3
  • 13
    • 0019543877 scopus 로고
    • An implicit enumeration algorithm to generate tests for combinational logic circuits
    • (1981) IEEE Trans. on Computer , vol.30 C , Issue.3 , pp. 215-222
    • Goel, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.