A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2003, Pages 156-157+500

  Morishita, Fukashl ^a   Hayashi, Isamu ^a   Matsuoka, Hideto ^a   Takahashi, Kazuhiro ^a   Shigata, Kuniyasu ^a   Gyohten, Takayuki ^a   Niiro, Mitsutaka ^a   Okamoto, Mako ^b   Hachisuka, Atsushi ^a   Amo, Atsushi ^a   Shinkawata, Hiroki ^a   Kasaoka, Tatsuo ^a   Dosaka, Katsumi ^a   Arimoto, Kazutami ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Daioh Electric   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DELAY CIRCUITS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; POWER CONTROL; SIMULATION; STANDBY POWER SYSTEMS; TIMING DEVICES; VOLTAGE MEASUREMENT;

DATA RETENTION POWER; EMBEDDED DRAM; TIMING CONTROL; TIMING GENERATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442659201     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)