Universal-Vdd 0.65-2.0V 32kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 168-169+443

  Osada, K ^a   Shin, J U ^a   Khan, M ^a   Liou, Y D ^a   Wang, K ^a   Shoji, K ^a   Kuroda, K ^a   Ikeda, S ^a   Ishibashi, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; PHOTOLITHOGRAPHY; SCANNING ELECTRON MICROSCOPY; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

LITHOGRAPHICAL-SYMMETRIC (LS) MEMORY CELLS;

BUFFER STORAGE;

EID: 0035055201     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A replica technique for wordline and sense control in low-power SRAM's
2. A 1.0ns access 770MHz 36Kb SRAM macro
3. 2 full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25μm-Generation CMOS technology