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Volumn , Issue , 2004, Pages 309-316

Proactive Design for Manufacturing (DFM) for nanometer SoC designs

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR MANUFACTURABILITY (DFM); ELECTRONIC DESIGN AUTOMATION (EDA); RANDOM MECHANISM LIMITED YIELD (RMY); SYSTEMATIC MECHANISM LIMITED YIELD (SMLY);

EID: 17044378430     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (22)

References (22)
  • 2
    • 2442653656 scopus 로고    scopus 로고
    • Interconnect limits on gigascale integration (GSI) in the 21st century
    • Mar
    • J. A. Davis et al, "Interconnect limits on gigascale integration (GSI) in the 21st century"; Proceedings of the IEEE, Volume: 89, Issue: 3, Mar 2001, pages: 305-324
    • (2001) Proceedings of the IEEE , vol.89 , Issue.3 , pp. 305-324
    • Davis, J.A.1
  • 3
    • 3042520522 scopus 로고    scopus 로고
    • Tests structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability
    • S. Saxena et al, "Tests Structures and Analysis Techniques for Estimation of the Impact of Layout on MOSFET Performance and Variability", ICMTS 2004
    • ICMTS 2004
    • Saxena, S.1
  • 4
    • 0030649703 scopus 로고    scopus 로고
    • Determination of defect size distributions based on electrical measurements at a novel harp test structure
    • March
    • C. Hess, L. Weiland, "Determination of Defect Size Distributions Based on Electrical Measurements at a Novel Harp Test Structure"; Proc. IEEE 1997 Int. Conference on Microelectronic Test Stuctures, Vol.10, March 1997
    • (1997) Proc. IEEE 1997 Int. Conference on Microelectronic Test Stuctures , vol.10
    • Hess, C.1    Weiland, L.2
  • 5
    • 0037481698 scopus 로고    scopus 로고
    • Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation
    • C. Hess et al, "Passive Multiplexer Test Structure for Fast and Accurate Contact and Via Fail Rate Evaluation", ICMTS 2002
    • ICMTS 2002
    • Hess, C.1
  • 6
    • 0035509187 scopus 로고    scopus 로고
    • Addressable Failure Site Test Structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation
    • Nov.
    • K. Doong et al, "Addressable Failure Site Test Structures (AFS-TS) for CMOS Processes: Design Guidelines, Fault Simulation, and Implementation", IEEE Trans. on Semiconductor Manufacturing, Vol. 14, Nov. 2001
    • (2001) IEEE Trans. on Semiconductor Manufacturing , vol.14
    • Doong, K.1
  • 7
    • 0038303483 scopus 로고    scopus 로고
    • Characterization and modeling of MOSFET mismatch of a deep submicron technology
    • M. Quarantelli et al, "Characterization and Modeling of MOSFET Mismatch of a Deep Submicron Technology", ICMTS 2003
    • ICMTS 2003
    • Quarantelli, M.1
  • 11
    • 0022680566 scopus 로고
    • CMOS test chip design for process problem debugging and yield prediction experiments
    • March
    • W. Lukaszek, W. Yarbrough, T. Walker, J. Meindl, "CMOS Test Chip Design for Process Problem Debugging and Yield Prediction Experiments", Solid State Technology, pp. 87-92, March 1986
    • (1986) Solid State Technology , pp. 87-92
    • Lukaszek, W.1    Yarbrough, W.2    Walker, T.3    Meindl, J.4
  • 12
    • 2942696340 scopus 로고    scopus 로고
    • Integrated electrical and SEM based defect characterization for rapid yield ramp
    • J. Orbon et al, "Integrated electrical and SEM based defect characterization for rapid yield ramp", SPIE 2004
    • SPIE 2004
    • Orbon, J.1
  • 15
    • 0020846899 scopus 로고
    • Modeling of integrated circuit defect sensitivites
    • November
    • C. H. Stapper, "Modeling of Integrated Circuit Defect Sensitivites", IBM J. Res. Develop., Vol. 27, No. 6, November, 1983
    • (1983) IBM J. Res. Develop. , vol.27 , Issue.6
    • Stapper, C.H.1
  • 16
    • 0021782318 scopus 로고
    • The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions
    • January
    • C. H. Stapper, "The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions", IBM J. Res. Develop., Vol. 29, No. 1, January 1985
    • (1985) IBM J. Res. Develop. , vol.29 , Issue.1
    • Stapper, C.H.1
  • 19
    • 84860106333 scopus 로고    scopus 로고
    • "Integrated circuit design to optimize manufacturability", US Patent pending
    • N. Dragone et al, "Integrated circuit design to optimize manufacturability", US Patent pending, 2003
    • (2003)
    • Dragone, N.1
  • 22
    • 17044373705 scopus 로고    scopus 로고
    • ATE solutions for the global semiconductor industry
    • Fabless Semiconductor Association, March
    • D. Hamling, "ATE Solutions For The Global Semiconductor Industry", Fabless Forum, Vol. 11, No. 1, Fabless Semiconductor Association, March 2004
    • (2004) Fabless Forum , vol.11 , Issue.1
    • Hamling, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.