Integrated electrical and SEM based defect characterization for rapid yield ramp

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5378, Issue , 2004, Pages 142-150

  Orbon, Jacob ^a   Levin, Lior ^a   Bokobza, Ofer ^a   Shimshi, Rinat ^a   Dutta, Manjari ^a   Zhang, Brian ^a   Ciplickas, Dennis ^b   Pham, Teri ^b   Jensen, Jim ^b  

^a APPLIED MATERIALS INC   (United States)

^b PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACK END OF THE LINE (BEOL); DEFECT CHARACTERIZATION; ELECTRICAL DEFECTS; RAPID YIELD RAMP;

DEFECTS; MICROPROCESSOR CHIPS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS; STATISTICAL METHODS;

FAILURE ANALYSIS;

EID: 2942696340     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.536469     Document Type: Conference Paper

References (6)

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2. Zstanojevic, H. Balachandran, D. M. H. Walker, F. Lakhani Sri Jandhyala "Defect Localization Using Physical Design and Electrical Test Information", Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI, 12-14 Sept. 2000, Page(s): 108-115
3. Lavo, D.B.; Chess, B.; Larrabee, T.; Ferguson, F.J.; "Diagnosing realistic bridging faults with single stuckat information", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 17 Issue: 3, Page(s): 255-268, March 1998
4. D. J. Ciplickas, B. Stine, Y. Fei, et. al., Test Structures and Models for Estimating the Yield Impact of Dishing and/or Voids, U.S. Provisional Patent Application No. 60/316, 317, filed August 31, 2001.
5. D. Ciplickas, S. Lee, C. Hess, L. Weiland, et. al., Fast Localization of Electrical Failures on an Integrated Circuit System and Method, U.S. Provisional Application No. 60/432, 786, filed December 11, 2002.
6. D. J. Ciplickas, X. Li, A. J. Strojwas, Predictive Yield Modeling of VLSICs, Proc. of IWSM 2000, Honolulu, HA, June 2000.