Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 263-266

  Saxena, Sharad ^a   Minehane, Seán ^a   Cheng, Jianjun ^a   Sengupta, Manidip ^a   Hess, Christopher ^a   Quarantelli, Michele ^a   Kramer, Glenn M ^a   Redford, Mark ^a  

^a PDF Solutions   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MECHANICAL STRESS; TRANSISTOR ARRAY TEST STRUCTURES;

ELECTRIC GENERATORS; LITHOGRAPHY; MOS DEVICES; OPTIMIZATION; PERFORMANCE; SENSITIVITY ANALYSIS; SILICON WAFERS; STATISTICAL METHODS; STRESS ANALYSIS;

MOSFET DEVICES;

EID: 3042520522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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