Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2002, Pages 163-167

  Hess, Christopher ^a   Stine, Brian E ^a   Weiland, Larg H ^a   Mitchell, Todd ^b   Karnett, Marty ^b   Gardner, Keith ^b  

^a PDF SOLUTIONS INC   (United States)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONTACTS; ELECTRIC RESISTANCE MEASUREMENT; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; TRANSISTORS;

FAIL RATE EVALUATION; MEASUREMENT PADS; PASSIVE MULTIPLEXER ARRAY; PASSIVE MULTIPLEXER TEST STRUCTURE;

INTEGRATED CIRCUIT TESTING;

EID: 0037481698     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icmts.2002.1193190     Document Type: Conference Paper

References (7)

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2. Hess, C., Weiland, L. H. Influence of Short Circuits on Data of Contact & Via Open Circuits Determined by a Novel Weave Test Structure IEEE Transactions on Semiconductor Manufacturing, pp. 27-34, Vol. 9, No. 1, 1996
3. Ipri, A. C., Sarace, J. C. Integrated Circuit Process and Design Rule Evaluation Techniques RCA Review pp. 323-350, Volume 38, Number 3, September 1977
4. Staper, C. H. Rosner, R. J. Integrated Circuit Yield Management and Yield Analysis: Development and Implementation IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995
5. Ward, D., Walton, A. J., Gammie, W. G., Holwill, R. J. The Use of a Digital Multiplexer to Reduce Process Control Chip Pad Count International Conference on Microelectronic Test Structures 1992, San Diego / USA, 1992
6. Walton, A. J., Gammie, W., Marrow, D., Stevenson, J. T. M., Holwill, R. J. A novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips International Conference on Microelectronic Test Structures, San Diego / USA, 1990
7. Walton, A. J., Ward, D., Robertson, J. M., Holwill R. J. A Novel Approach for an Electrical Vernier to Measure Mask Misalignment 19th European Solid State Device Research Conference ESSDERC '89, Springer Verlag, 1989