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Volumn , Issue , 2004, Pages 123-126

Module placement for power supply noise and wire congestion avoidance in 3D packaging

Author keywords

[No Author keywords available]

Indexed keywords

CONGESTION AVOIDANCE; POWER SUPPLY NOISE; SIMULTANEOUS SWITCHING NOISE (SSN); THREE DIMENSIONAL (3D) PACKAGING;

EID: 15944372883     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (11)
  • 5
    • 0036179950 scopus 로고    scopus 로고
    • Decoupling capacitance allocation and its application to power supply noise aware floorplanning
    • S. Zhao, C.-K. Koh, and K. Roy, "Decoupling capacitance allocation and its application to power supply noise aware floorplanning," IEEE Trans. on Computer-Aided Design, pp. 81-92, 2002.
    • (2002) IEEE Trans. on Computer-aided Design , pp. 81-92
    • Zhao, S.1    Koh, C.-K.2    Roy, K.3
  • 6
    • 0033878239 scopus 로고    scopus 로고
    • A methodology for the placement and optimization of decoupling capacitors for gigahertz systems
    • J. Choi, S. Chun, N. Na, M. Swaminathan, and L. Smith, "A methodology for the placement and optimization of decoupling capacitors for gigahertz systems," in VLSI Design Symposium, 2000.
    • (2000) VLSI Design Symposium
    • Choi, J.1    Chun, S.2    Na, N.3    Swaminathan, M.4    Smith, L.5
  • 7
    • 0036374252 scopus 로고    scopus 로고
    • An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
    • H. Su, S. Sapatnekar, and S. R. Nassif, "An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts," in Proc. Int. Symp. on Physical Design, 2002, pp. 68-73.
    • (2002) Proc. Int. Symp. on Physical Design , pp. 68-73
    • Su, H.1    Sapatnekar, S.2    Nassif, S.R.3
  • 9


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.