-
2
-
-
3042662116
-
Net and pin distribution for 3D package global routing
-
J. Minz, M. Pathak, and S. K. Lim, "Net and pin distribution for 3D package global routing," in Proc. Design, Automation and Test in Europe, 2004.
-
(2004)
Proc. Design, Automation and Test in Europe
-
-
Minz, J.1
Pathak, M.2
Lim, S.K.3
-
3
-
-
10444236433
-
Physical layout automation for system-on-packages
-
R. Ravichandran, J. Minz, M. Pathak, S. Easwar, and S. K. Lim, "Physical layout automation for system-on-packages," in IEEE Electronic Components and Technology Conference, 2004.
-
(2004)
IEEE Electronic Components and Technology Conference
-
-
Ravichandran, R.1
Minz, J.2
Pathak, M.3
Easwar, S.4
Lim, S.K.5
-
4
-
-
4344688812
-
Multi-layer floorplanning for reliable system-on-package
-
P. H. Shiu, R. Ravichandran, S. Easwar, and S. K. Lim, "Multi-layer floorplanning for reliable system-on-package," in Proc. IEEE Int. Symp. on Circuits and Systems, 2004.
-
(2004)
Proc. IEEE Int. Symp. on Circuits and Systems
-
-
Shiu, P.H.1
Ravichandran, R.2
Easwar, S.3
Lim, S.K.4
-
5
-
-
0036179950
-
Decoupling capacitance allocation and its application to power supply noise aware floorplanning
-
S. Zhao, C.-K. Koh, and K. Roy, "Decoupling capacitance allocation and its application to power supply noise aware floorplanning," IEEE Trans. on Computer-Aided Design, pp. 81-92, 2002.
-
(2002)
IEEE Trans. on Computer-aided Design
, pp. 81-92
-
-
Zhao, S.1
Koh, C.-K.2
Roy, K.3
-
6
-
-
0033878239
-
A methodology for the placement and optimization of decoupling capacitors for gigahertz systems
-
J. Choi, S. Chun, N. Na, M. Swaminathan, and L. Smith, "A methodology for the placement and optimization of decoupling capacitors for gigahertz systems," in VLSI Design Symposium, 2000.
-
(2000)
VLSI Design Symposium
-
-
Choi, J.1
Chun, S.2
Na, N.3
Swaminathan, M.4
Smith, L.5
-
7
-
-
0036374252
-
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
-
H. Su, S. Sapatnekar, and S. R. Nassif, "An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts," in Proc. Int. Symp. on Physical Design, 2002, pp. 68-73.
-
(2002)
Proc. Int. Symp. on Physical Design
, pp. 68-73
-
-
Su, H.1
Sapatnekar, S.2
Nassif, S.R.3
-
8
-
-
84954410160
-
Floorplanning with power supply noise avoidance
-
H. Chen, L. Huang, I. Liu, M. Lai, and D. Wong, "Floorplanning with power supply noise avoidance," in Proc. Asia and South Pacific Design Automation Conf., 2003.
-
(2003)
Proc. Asia and South Pacific Design Automation Conf.
-
-
Chen, H.1
Huang, L.2
Liu, I.3
Lai, M.4
Wong, D.5
-
9
-
-
26444479778
-
Optimization by simulated annealing
-
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, pp. 671-680, 1983.
-
(1983)
Science
, pp. 671-680
-
-
Kirkpatrick, S.1
Gelatt, C.D.2
Vecchi, M.P.3
-
10
-
-
0029488327
-
Rectangle packing based module placement
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle packing based module placement," in Proc. IEEE Int. Conf. on Computer-Aided Design, 1995, pp. 472-479.
-
(1995)
Proc. IEEE Int. Conf. on Computer-aided Design
, pp. 472-479
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
11
-
-
0036479019
-
Modeling and simulation of core switching noise for asics
-
N. Na, J. Choi, M. Swaminathan, J. P. Libous, and D. P. O'Connor, "Modeling and simulation of core switching noise for asics," IEEE Trans. Advanced Packaging, pp. 4-11, 2002.
-
(2002)
IEEE Trans. Advanced Packaging
, pp. 4-11
-
-
Na, N.1
Choi, J.2
Swaminathan, M.3
Libous, J.P.4
O'Connor, D.P.5
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