Multi-layer floorplanning for reliable system-on-package

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Shiu, Pun Hang ^a   Ravichandran, Ramprasad ^a   Easwar, Siddharth ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN CONSTRAINTS; EMBEDDED PASSIVE COMPONENTS (EPC); SIGNAL INTEGRITY; SYSTEM-ON-PACKAGE (SOP) TECHNOLOGY;

AUTOMATION; CAPACITORS; INTEGRATED CIRCUIT LAYOUT; INTEGRATION; RESISTORS; SIGNAL THEORY;

ELECTRONICS PACKAGING;

EID: 4344688812     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. Y. Deng and W. Maly, "Interconnect characteristics of 2.5-D system integration scheme," Int. Symposium on Physical Design, 2001, Apr. 2001.
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4. H. Murata, K. Fujiyoshi, et al., "VLSI module placement based on rectangle-packing by the sequence pair," IEEE Transaction on CAD, vol. 15:12, pp. 1518-1524, 1996.
5. E. F. Y. Young, C. C. N. Chu, M. L. Ho, "A unified method to handle different kinds of placement constraints in floorplan design," ACM Design Automation Conf, 2002. pp. 661-667
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7. Xiaoping Tang, D. F. Wong, "Floorplanning width Alignment and Performance Constraints," ACM Design Automation Conf., 2002.