Layer assignment for reliable system-on-package

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 31-37

  Minz, Jacob R ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOORPLANS; LAYER-SWITCH NODES; ROUTING INTERVALS; SYSTEM ON PACKAGE (SOP);

ALGORITHMS; COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; ELECTRONICS PACKAGING; MICROELECTROMECHANICAL DEVICES; OPTOELECTRONIC DEVICES; ROUTERS; SYSTEMS ANALYSIS; TOPOLOGY;

COMPUTER SCIENCE;

EID: 2442517497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Rao Tummala and Vijay Madisetti, "System on Chip or System on Package?", IEEE Design & Test of Computers, pp 48-56, 1999.
2. J. Cong, Pin assignment with global routing for general cell designs, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 10 Issue: 11, Nov 1991, Page(s): 1401-1412
3. C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng, and D. Karger, Prim-Dijkstra tradeoffs for improved performance-driven routing tree design, IEEE Trans. on CAD 14(7), July 1995, pp.890-896
4. M. Borah, R. M. Owens, and M. J. Irwin, An edge-based heuristic for Steiner routing, in IEEE Trans. on CAD, vol. 13, no. 12, Dec. 1994, pp. 1563-1568.
5. A. B. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance", IEEE Trans. on CAD 11 (7), July 1992, pp. 893-902
6. J. Cong, A.B. Kahng, K Leung, Efficient Algorithms for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design, IEEE Trans. on CAD, vol. 17, no.1, January 1998
7. Ho, M. Sarrafzadeh, G. Vijayan, C. Wong, "Layer assignment for multi-chip modules", IEEE Transactions on Computer-Aided Design, Vol. 9, No. 12, December 1990, pp. 1272-1277
8. M. Sriram and S. M. Kang, "Detailed Layer Assignment for MCM Routing," Proc. of ICCAD, pp. 386-389, 1992.
9. J. CHo, M. Sarrafzadeh, M. Sriram, S. Kang, High Performance MCM Routing, IEEE Design & Test of Computers, 1993
10. Joy, D.A.; Ciesielski, M.J., "Layer assignment for printed circuit boards and integrated circuits", Proceedings of the IEEE, Vol 80, pp 311-331, Feb 1992.
11. Rao Tummala, "Multichip packaging-a tutorial", Proceedings of the IEEE, pp 1924-1941, 1992.
12. Jason Cong and Sung Kyu Lim, "Physical Planning with Retiming", IEEE International Conference on Computer Aided Design, p2-7, 2000.