High-performance poly-Si TFTs fabricated by implant-to-silicide technique

IEEE Electron Device Letters

Volumn 26, Issue 3, 2005, Pages 185-187

  Lin, Chia Pin ^a   Xiao, Yi Hsuan ^a   Tsui, Bing Yue ^a,b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Implant to silicide (ITS); Silicide source drain (S D); Thin film transistor (TFT)

Indexed keywords

CARRIER MOBILITY; CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; LEAKAGE CURRENTS; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; THRESHOLD VOLTAGE;

IMPLANT-TO-SILICIDE (ITS); LOW PRESSURE CHEMICAL VAPOR DEPOSITION; SHALLOW EXTENSION; SILICIDE SOURCE/DRAIN (S/D);

THIN FILM TRANSISTORS;

EID: 15544380878     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.843929     Document Type: Article

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