A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

IEEE Electron Device Letters

Volumn 22, Issue 8, 2001, Pages 393-395

  Zhang, Shengdong ^b,c   Han, Ruqi ^b,c   Chan, Mansun J ^a,b,c  

^a IEEE

^b PEKING UNIVERSITY   (China)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Bottom gate; LDD; Self aligned structure; Thin film transistor

Indexed keywords

CHEMICAL VAPOR DEPOSITION; ELECTRON MOBILITY; GATES (TRANSISTOR); ION IMPLANTATION; LITHOGRAPHY; MASKS; POLYSILICON; SEMICONDUCTING FILMS; SEMICONDUCTOR DOPING; SILICON WAFERS; SUBSTRATES;

SELF-ALIGNED STRUCTURES;

THIN FILM TRANSISTORS;

EID: 0035425241     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.936354     Document Type: Article

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