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Volumn 2003-January, Issue , 2003, Pages 48-53

A 225 MHz resonant clocked ASIC chip

Author keywords

Application specific integrated circuits; Clocks; CMOS process; Discrete wavelet transforms; Flip flops; Frequency; Power measurement; Resonance; Signal generators; Testing

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DISCRETE WAVELET TRANSFORMS; ELECTRIC CLOCKS; ELECTRIC POWER MEASUREMENT; ENERGY CONSERVATION; FLIP FLOP CIRCUITS; LOW POWER ELECTRONICS; POWER ELECTRONICS; RECOVERY; RESONANCE; SIGNAL GENERATORS; TESTING; WAVELET TRANSFORMS;

EID: 1542329513     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231834     Document Type: Conference Paper
Times cited : (20)

References (8)
  • 3
    • 0034244994 scopus 로고    scopus 로고
    • Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
    • Aug.
    • D. Maksimovic, V. G. Oklobdzija, B. Nikolic, and K. W. Current, "Clocked CMOS adiabatic logic with integrated single-phase power-clock supply," IEEE Transactions on VLSI Systems, vol. 8, no. 4, pp. 460-463, Aug. 2000.
    • (2000) IEEE Transactions on VLSI Systems , vol.8 , Issue.4 , pp. 460-463
    • Maksimovic, D.1    Oklobdzija, V.G.2    Nikolic, B.3    Current, K.W.4
  • 5
    • 0035429510 scopus 로고    scopus 로고
    • Conditional-capture flip-flop for statistical power reduction
    • Aug
    • B.S. Kong, S.S. Kim, and Y.H. Jun, "Conditional-capture flip-flop for statistical power reduction," IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, Aug. 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.8 , pp. 1263-1271
    • Kong, B.S.1    Kim, S.S.2    Jun, Y.H.3
  • 6
  • 7
    • 0033116422 scopus 로고    scopus 로고
    • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
    • Apr.
    • V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE Journal of Sold-State Circuits, vol. SC-34, no. 4, pp. 536-548, Apr. 1999.
    • (1999) IEEE Journal of Sold-State Circuits , vol.SC-34 , Issue.4 , pp. 536-548
    • Stojanovic, V.1    Oklobdzija, V.G.2
  • 8
    • 0030828211 scopus 로고    scopus 로고
    • New single-clock CMOS latches and flipflops with improved speed and power savings
    • Jan.
    • J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings," IEEE Journal of Solid-State Circuits, vol. SC-32, no. 1, pp. 62-69, Jan. 1997.
    • (1997) IEEE Journal of Solid-State Circuits , vol.SC-32 , Issue.1 , pp. 62-69
    • Yuan, J.1    Svensson, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.