Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 4, 2000, Pages 460-463

  Maksimović, Dragan ^a   Oklobdžija, Vojin G ^b   Nikolić, Borivoje ^c   Current, K Wayne ^d  

^a University of Colorado at Boulder   (United States)

^b Integration Corporation   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d University of California Davis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; POWER CONTROL; TRANSISTORS; WAVEFORM ANALYSIS;

CLOCKED ADIABATIC LOGIC (CAL) CIRCUITS; LOW-POWER COMPUTING;

VLSI CIRCUITS;

EID: 0034244994     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.863629     Document Type: Article

References (16)

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