Energy recovering ASIC design

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 133-138

  Ziesler, Conrad H ^a   Kim, Joohee ^a   Papaefthymiou, Marios C ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Application specific integrated circuits; Clocks; Computer architecture; Design methodology; Energy consumption; Flip flops; Inductors; Laboratories; Resonance; Voltage

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPLEX NETWORKS; COMPUTER ARCHITECTURE; DESIGN; ELECTRIC CLOCKS; ELECTRIC INDUCTORS; ELECTRIC POTENTIAL; ENERGY CONSERVATION; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; LABORATORIES; RECOVERY; RESONANCE;

CLOCKING SCHEMES; DESIGN METHODOLOGY; ENERGY RECOVERING; OPERATING VOLTAGE; REDUCING ENERGY CONSUMPTION; RESONANT CLOCK; SWITCHING ACTIVITIES; TOTAL ENERGY CONSUMPTION;

CLOCKS;

EID: 0038791336     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183364     Document Type: Conference Paper

References (9)

1. B.S. Kong, S.S. Kim, and Y.H. Jun, "Conditional-capture flip-flop for statistical power reduction," IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, Aug. 2001.
2. V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE Journal of Sold-State Circuits, vol. SC-34, no. 4, pp. 536-548, Apr. 1999.
3. J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings," IEEE Journal of Solid-State Circuits, vol. SC-32, no. 1, pp. 62-69, Jan. 1997.
4. W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and Y. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 398-406, Dec. 1994.
5. D. Maksimovic, V. G. Oklobdzija, B. Nikolic, and K. W. Current, "Clocked CMOS adiabatic logic with integrated single-phase power-clock supply," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 460-463, Aug. 2000.
6. C. H. Ziesler, S. Kim, and M. C. Papaefthymiou, "A power-clock generator for true single-phase adiabatic logic," in Proceedings of International Symposium on Low-Power Electronics and Design, Aug. 2001, pp. 159-164.
7. J. S. Moon, W. C. Athas, and P. A. Beerel, "Theory and practical implementation of harmonic resonant rail drivers," in Proceedings of the International Symposium of Low-Power Electronics and Design, Aug. 2001, pp. 153-158.
8. W. Athas, N. Tzartzanis, W. Mao, L. Peterson, R. Lal, K. Chong, J.S. Moon, L. Svensson, and M. Bolotski, "The design and implementation of a low-power clock-powered microprocessor," IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1561-1570, Nov. 2000.
9. S. Kim, C. H. Ziesler, and M. C. Papaefthymiou, "A true single-phase adiabatic multiplier," in Proceedings of 38th Design Automation Conference, June 2001, pp. 758-763.