A low-swing clock double-edge triggered flip-flop

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 183-186

  Kim, C ^a   Kang, S M ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; MICROPROCESSOR CHIPS; MOSFET DEVICES; VLSI CIRCUITS;

EDGE TRIGGERED FILP-FLOPS;

FLIP FLOP CIRCUITS;

EID: 0034794610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Flow-through latch and edge-triggered flip-flop hybrid elements
2. Semi-dynamic and dynamic flip-flops with embedded logic
3. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
4. Conditional-capture flip-flop technique for statistical power reduction
5. Half-swing clocking scheme for 75% power saving in clocking circuitry
6. A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% clock power reduction
7. Design of a 3-V 300-MHz low-power 8-b × 8-b pipelined multiplier using pulse-triggered TSPC flip-flops