A 1.8-GHz instruction window buffer for an out-of-order microprocessor core

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1628-1635

  Leenstra, Jens ^b   Pille, Jürgen ^b   Müller, Antje ^b   Sauer, Wolfram M ^a,b   Sautter, Rolf ^b   Wendel, Dieter F ^b  

^a IEEE

^b IBM   (Germany)

Author keywords

CMOS integrated circuits; Computer architecture; High speed integrated circuits; Integrated circuit design; Logic design; Microprocessors

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COPPER; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN;

HIGH SPEED INTEGRATED CIRCUITS; INSTRUCTION WINDOW BUFFER; MICROPROCESSOR DESIGNS;

MICROPROCESSOR CHIPS;

EID: 0035505582     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962282     Document Type: Article

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11. A 1.8-GHz instruction window buffer