Global Interconnect Trade-off For Technology Over Memory Modules To Application Level: Case Study

International Workshop on System Level Interconnect Prediction

Volumn , Issue , 2003, Pages 125-132

  Papanikolaou, A ^a   Miranda, M ^a   Catthoor, F ^b   Corporaal, H ^c   De Man, H ^b   De Roest, D ^a   Stucchi, M ^a   Maex, Karen ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Interconnect wire processing; Intra inter memory interconnect; Pareto optimal energy delay interconnect exploration

Indexed keywords

CAPACITANCE; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; DATA TRANSFER; ELECTRIC RESISTANCE; LOGIC DESIGN; PARALLEL PROCESSING SYSTEMS; SYSTEMS ANALYSIS;

DELAY INTERCONNECT EXPLORATION; INTERCONNECT WIRE PROCESSING; INTRA/INTER-MEMORY INTERCONNECT; PARETO-OPTIMAL ENERGY;

INTERCONNECTION NETWORKS;

EID: 1442327876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)

1. D. Sylvester, K. Keutzer, Impact of small process geometries on microarchitectures in systems on a chip, Proceedings of the IEEE, vol.89, no.4, p. 467, April 2001.
2. J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S.J. Shouri, K. Banerjee, K.C. Saraswat, A. Rahman, R. Reif, J.D. Meindl, Interconnect limits on gigascale integration (GSI) in the 21st century, Proceedings of the IEEE, no.3, vol.89, pp. 305, March 2001.
3. Ankireddy Nalamalpu and Wayne Burleson, Repeater Insertion in deep sub-micron CMOS: Ramp-based Analytical Model and Placement Sensitivity Analysis, Proceedings of International Symposium on Circuits and Systems, June 2000.
4. D. Sylvester, C. Hu, O.S. Nakagawa, and S-Y. Oh, Interconnect scaling: signal integrity and performance in future high-speed CMOS designs, Proceedings Of Symposium on VLSI Technology, pp. 42-43, 1998.
5. B.Gordon, E.Tsern, T.H.Meng, Design of a low power video decompression chip set for portable applications J. of VLSI signal processing, No.13, Kluwer, Boston, pp. 125-142, 1996.
6. R.Gonzales, M.Horowitz, Energy dissipation in general-purpose microprocessors IEEE Journal of Solid-state Circ., Vol.SC-31, No.9, pp.1277-1283, Sep. 1996.
7. F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, A. Vandecappelle Custom memory management methodology exploration of memory organization for embedded multimedia system design Kluwer, June 1998.
8. F.Catthoor, K.Danckaert, C.Kulkarni, E.Brockmeyer, P.G.Kjeldsberg, T.Van Achteren, T.Omnes, Data access and storage management for embedded programmable processors, ISBN 0-7923-7689-7, Kluwer Acad. Publ., Boston, 2002.
9. Steven J. E. Wilton and Norman P. Jouppi "CACTI: An Enhanced Cache Access and Cycle Time Model" IEEE Journal of Solid-State Circuits, Vol.32, No.5, pp.677-687, May 1996.
10. P. Op de Beeck, C. Ghez, E. Brockmeyer, M. Miranda, F. Catthoor, G. Deconinck Low-Power Implementation of an OFDM based Channel Receiver in Real-Time Using a Low-end Media Processor, IEEE CAS Workshop on Wireless Communications and Networking, Pasadena CA, Sept. 2002.
11. K.Itoh, "Low Voltage Memory Design", in tutorial on "Low voltage technologies and circuits", IEEE Intnl. Symp. on Low Power Design, Monterey CA, Aug. 1997.
12. K.Itoh, "Low-Voltage Memories for Power-aware Systems", IEEE Intnl. Symp. on Low Power Design, Monterey CA, pp.1-6, Aug. 2002.
13. A.Chatzigeorgiou, S.Nikolaidis, "Reducing power consumption in memories", in "Designing CMOS circuits for low power" (eds. D.Soudris, C.Piguet, C.Goutis), pp.117-140, Kluwer Acad. Publ., Boston, 2002.
14. R.Evans, P.Franzon, "Energy consumption modeling and optimization for SRAMs", IEEE J. of Solid-state Circ., Vol.SC-30, No.5, pp.571-579, May 1995.
15. Teruo Seki, Eisaki Itoh, Chiaki Furukawa, Isamu Maeno, Tadashi Ozawa, Hiroyuki Sano and Noriyuki Suzuki, A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier, IEEE Journal of Solid-State Circuits, no.4, vol.28, pp. 478, April 1993.
16. I.Saeed, "Integrated memory ups speed, saves power", Electronic Engineering Times, pp.94, April 28, 1997.
17. D.A.Patterson, T.Anderson, N.Cardwell, R.Fromm, K.Keeton, C.Kozyrakis, R.Thomas, K.Yelick, "Intelligent RAM (IRAM): chips that remember and compute", Proc. IEEE Intnl. Solid-State Circ. Conf., San Francisco CA, pp.224-225, Feb. 1997.
18. A.Macii, L.Benini, M.Poncino, "Memory Design Techniques for Low Energy Embedded Systems". ISBN 0-7923-7690-0, Kluwer Acad. Publ., Boston, 2002.
19. P.R.Panda, N.D.Dutt, A.Nicolau, "Memory issues in embedded in systems-on-chip: optimization and exploration", Kluwer Acad. Publ., Boston, 1999.
20. International Technology Roadmap for Semiconductors 2001, http://public.itrs.net.
21. D. A. B. Miller, Rationale and Challenges for Optical Interconnects to Electronic Chips, Proceedings of the IEEE, no.6, vol.88, pp. 728-749, June 2000.
22. Avant! TCAD, Raphael Interconnect Analysis Program, Version 2002.2 Reference Manual, June 2002.
23. E.Brockmeyer, A.Vandecappelle, F.Catthoor. Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications Proc. IEEE Int. Symp. on Low Power Electronics and Design, pages 137-142, Rapallo, Italy, Aug. 2000.
24. http://research.compaq.com/wrl/people/jouppi/CACTI.html
25. M. A. Horowitz, "Timing models for MOS circuits", Integrated Circuits Lab., Stanford Univ., Tech. Report SEL83-003, 1983
26. Motomu Ukita, Shuji Murakami, Tadato Yamagata, Hirotada Kuriyama, Yasumasa Nishimura and Kenji Anami, A Single-Bit-Line Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAM's, IEEE Journal of Solid-State Circuits, no.11, vol.28, pp. 1114, November 1993.
27. B. Amrutur, M.A. Horowitz, Speed and power scaling of SRAM's IEEE Transactions on Solid State Circuits, vol. 35, no. 2, p. 175, February 2000
28. A.Vandecappelle, M.Miranda, E.Brockmeyer F.Catthoor, D.Verkest, Global Multimedia System Design Exploration using Accurate Memory Organization Feedback Proc. 36th ACM/IEEE Design Automation Conf., New Orleans LA. pp.327-332, June 1999.
29. Atomium project web site http://www.imec.be/atomium/ or http://www.imec.be/design/multimedia/atomium/.