Fast instruction set customization

Proceedings of the 2004 2nd Workshop on Embedded Systems for Real-Time Multimedia

Volumn , Issue , 2004, Pages 53-58

  Borin, Edson ^a   Klein, Felipe ^a   Moreano, Nahri ^a,b   Azevedo, Rodolfo ^a   Araujo, Guido ^a  

^a UNIVERSITY OF CAMPINAS   (Brazil)

^b FEDERAL UNIVERSITY OF MATO GROSSO DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; DECODING; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; GRAPH THEORY; MATHEMATICAL MODELS; PROGRAM COMPILERS;

CLUSTER CONSTRUCTION; CUSTOMIZATION; INSTRUCTION SET ARCHITECTURE (ISA); INSTRUCTION SET PROCESSORS (ASIP);

EMBEDDED SYSTEMS;

EID: 14244257987     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. M. Arnold and H. Corporaal. Designing domain-specific processors. In CODES, pp. 61-66, 2001.
2. K. Atasu, L. Pozzi, and P. Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. In DAC, pp. 256-261, 2003.
3. P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh. Instruction generation and regularity extraction for reconfigurable processors. In CASES, pp. 262-269, 2002.
4. N. Cheung, S. Parameswaran, and J. Henkel. INSIDE: Instruction selection/identification & design exploration for extensible processors. In ICCAD, pp. 291-297, 2003.
5. H. Choi, J. Kim, C. Yoon, I. Park, S. Hwang, and C. Kyung. Synthesis of application specific instructions for embedded DSP software. IEEE Transactions on Computers, 48(6):603-614, 1999.
6. N. Clark, H. Zhong, W. Tang, and S. Mahlke. Automatic design of application specific instruction set extensions through dataflow graph exploration. International Journal of Parallel Programming, 31(6):429-449, 2003.
7. M. Garey and D. Johnson. Computers and Intractability -A Guide to the Theory of NP-Completeness. Freeman and CO., 1979.
8. D. Goodwin and D. Petkov. Automatic generation of application specific processors. In CASES, pp. 137-147, 2003.
9. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. Mibench: A free, commercially representative embedded benchmark suite. In WWC, pp. 3-14, 2001.
10. J. Hennessy, D. Patterson, and D. Goldberg. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, 2002.
11. I. Huang and A. Despain. Synthesis of application specific instruction sets. IEEE TCAD, 14(6):663-675, 1995.
12. R. Kastner, A. Kaplan, S. Ogrenci Memik, and E. Bozorgzadeh. Instruction generation for hybrid reconfigurable systems. ACM TODAES, 7(4):605-627, 2002.
13. A. La Rosa, L. Lavagno, and C. Passerone. Hardware/software design space exploration for a reconfigurable processor. In DATE, pp. 570-575, 2003.
14. C. Lee, M. Potkonjak, and W. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communication systems. In MICRO, pp. 330-335, 1997.
15. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.
16. S. Rigo, G. Araujo, M. Bartholomeu, and R. Azevedo. ArchC: A SystemC-based architecture description language. Accepted for publication at the 16th Symposium on Computer Architecture and High Performance Computing (SBAC), 2004. See http://www.archc.org.
17. R. Stallman. GNU Compiler Collection Internals, 2002.
18. F. Sun, S. Ravi, A. Raghunathan, and N. Jha. Custom-instruction synthesis for extensible-processor platforms. IEEE TCAD, 23(2):216-228, 2004.
19. J. Van Praet, G. Goossens, D. Lanneer, and H. De Man. Instruction set definition and instruction selection for ASIPs. In Proceedings of the 7th International Symposium on High-level Synthesis, pp. 11-16, 1994.