-
1
-
-
0036504519
-
Power4 system design for high reliability
-
D.C. Bossen, J.M. Tendler, and K. Reick. Power4 system design for high reliability. IEEE Micro, 22(2):16-24, 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 16-24
-
-
Bossen, D.C.1
Tendler, J.M.2
Reick, K.3
-
2
-
-
0034581565
-
Quantifying the SMT layout overhead- does SMT pull its weight?
-
J. Burns and J-L. Gaudiot. Quantifying the SMT layout overhead- does SMT pull its weight? In Proc. HPCA-6, pages 109-120, 2000.
-
(2000)
Proc. HPCA-6
, pp. 109-120
-
-
Burns, J.1
Gaudiot, J.-L.2
-
3
-
-
0242339538
-
Improving memory latency aware fetch policies for SMT processors
-
October
-
F. J. Cazorla, E. Fernandez, A. Ramirez, and M. Valero. Improving memory latency aware fetch policies for SMT processors. In Proc. ISHPC-5, pages 70-85, October 2003.
-
(2003)
Proc. ISHPC-5
, pp. 70-85
-
-
Cazorla, F.J.1
Fernandez, E.2
Ramirez, A.3
Valero, M.4
-
6
-
-
29144455318
-
Predictable performance in SMT processors
-
F.J. Cazorla, P.M.W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez, and M. Valero. Predictable performance in SMT processors. In Proc. Computing Frontiers, 2004.
-
(2004)
Proc. Computing Frontiers
-
-
Cazorla, F.J.1
Knijnenburg, P.M.W.2
Sakellariou, R.3
Fernandez, E.4
Ramirez, A.5
Valero, M.6
-
7
-
-
34547715869
-
Front-end policies for improved issue efficiency in SMT processors
-
A. El-Moursy and D.H. Albonesi. Front-end policies for improved issue efficiency in SMT processors. In Proc. HPCA-9, pages 31-42, 2003.
-
(2003)
Proc. HPCA-9
, pp. 31-42
-
-
El-Moursy, A.1
Albonesi, D.H.2
-
8
-
-
2342515986
-
A low complexity, high-performance fetch unit for simultaneous multithreading processors
-
February
-
Ayose Falcon, Alex Ramirez, and Mateo Valero. A low complexity, high-performance fetch unit for simultaneous multithreading processors. Proceedings of the 12th Intl. Conference on High Performance Computer Architecture, pages 244-253, February 2004.
-
(2004)
Proceedings of the 12th Intl. Conference on High Performance Computer Architecture
, pp. 244-253
-
-
Falcon, A.1
Ramirez, A.2
Valero, M.3
-
10
-
-
0026869325
-
An elementary processor architecture with simultaneous instruction issuing from multiple threads
-
H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa. An elementary processor architecture with simultaneous instruction issuing from multiple threads. In Proc. ISCA-19, pages 136-145, 1992.
-
(1992)
Proc. ISCA-19
, pp. 136-145
-
-
Hirata, H.1
Kimura, K.2
Nagamine, S.3
Mochizuki, Y.4
Nishimura, A.5
Nakase, Y.6
Nishizawa, T.7
-
11
-
-
0036995247
-
Soft real-time scheduling on simultaneous multithreaded processors
-
R. Jain, C.J. Hughes, and S.V. Adve. Soft real-time scheduling on simultaneous multithreaded processors. In Proc. RTSS-23, pages 134-145, 2002.
-
(2002)
Proc. RTSS-23
, pp. 134-145
-
-
Jain, R.1
Hughes, C.J.2
Adve, S.V.3
-
12
-
-
3042669130
-
IBM power5 chip: A dual-core multithreaded processor
-
R. Kalla, B. Sinharoy, and J. Tendler. IBM Power5 chip: A dual-core multithreaded processor. IEEE Micro, 24(2):40-47, 2004.
-
(2004)
IEEE Micro
, vol.24
, Issue.2
, pp. 40-47
-
-
Kalla, R.1
Sinharoy, B.2
Tendler, J.3
-
13
-
-
13944271663
-
Branch classification for SMT fetch gating
-
P.M.W. Knijnenburg, A. Ramirez, J. Larriba, and M. Valero. Branch classification for SMT fetch gating. In MTEAC-6, pages 49-56, 2002.
-
(2002)
MTEAC-6
, pp. 49-56
-
-
Knijnenburg, P.M.W.1
Ramirez, A.2
Larriba, J.3
Valero, M.4
-
14
-
-
4644332883
-
Multithreaded technologies disclosed at MPF
-
November
-
M. Levy. Multithreaded technologies disclosed at MPF. Microprocessor Report, November 2003.
-
(2003)
Microprocessor Report
-
-
Levy, M.1
-
15
-
-
0034825813
-
Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor
-
C. Limousin, J. Sebot, A. Vartanian, and N. Drach-Temam. Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor. In Proc. ICS-15, pages 236-245, 2001.
-
(2001)
Proc. ICS-15
, pp. 236-245
-
-
Limousin, C.1
Sebot, J.2
Vartanian, A.3
Drach-Temam, N.4
-
16
-
-
84962144701
-
Balancing throughput and fairness in SMT processors
-
K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In Proc. IS-PASS, pages 164-171, 2001.
-
(2001)
Proc. IS-PASS
, pp. 164-171
-
-
Luo, K.1
Gummaraju, J.2
Franklin, M.3
-
17
-
-
0001087280
-
Hyper-threading technology architecture and microarchitecture
-
February
-
D. T. Marr, F. Binns, D.L. Hill, G. Hinton, D.A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 6(1), February 2002.
-
(2002)
Intel Technology Journal
, vol.6
, Issue.1
-
-
Marr, D.T.1
Binns, F.2
Hill, D.L.3
Hinton, G.4
Koufaty, D.A.5
Miller, J.A.6
Upton, M.7
-
18
-
-
84968718478
-
The impact of resource partitioning on SMT processors
-
S. E. Raasch and S. K. Reinhardt. The impact of resource partitioning on SMT processors. In Proc. PACT-12, pages 15-25, 2003.
-
(2003)
Proc. PACT-12
, pp. 15-25
-
-
Raasch, S.E.1
Reinhardt, S.K.2
-
19
-
-
0034443570
-
Symbiotic job scheduling, with priorities for a simultaneous multithreaded processor
-
A. Snavely, D.M. Tullsen, and G. Voelker. Symbiotic job scheduling, with priorities for a simultaneous multithreaded processor. In Proc. ASPLOS-9, pages 234-244, 2000.
-
(2000)
Proc. ASPLOS-9
, pp. 234-244
-
-
Snavely, A.1
Tullsen, D.M.2
Voelker, G.3
-
20
-
-
0035696665
-
Handling long-latency loads in a simultaneous multithreaded processor
-
D. Tullsen and J. Brown. Handling long-latency loads in a simultaneous multithreaded processor. In Proc. MICRO-34, pages 318-327, 2001.
-
(2001)
Proc. MICRO-34
, pp. 318-327
-
-
Tullsen, D.1
Brown, J.2
-
21
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proc. ISCA-23, pages 191-202, 1996.
-
(1996)
Proc. ISCA-23
, pp. 191-202
-
-
Tullsen, D.1
Eggers, S.2
Emer, J.3
Levy, H.4
Lo, J.5
Stamm, R.6
-
22
-
-
0029200683
-
Simultaneous multithreading: Maximizing on-chip parallelism
-
D.M. Tullsen, S. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proc. ISCA, pages 392-403, 1995.
-
(1995)
Proc. ISCA
, pp. 392-403
-
-
Tullsen, D.M.1
Eggers, S.2
Levy, H.M.3
-
23
-
-
0029179466
-
Increasing superscalar performance through multistreaming
-
W. Yamamoto and M. Nemirovsky. Increasing superscalar performance through multistreaming. In Proc. PACT-4, pages 49-58, 1995.
-
(1995)
Proc. PACT-4
, pp. 49-58
-
-
Yamamoto, W.1
Nemirovsky, M.2
-
24
-
-
0032651228
-
Speculation techniques for improving load related instruction scheduling
-
May
-
A. Yoaz, M. Erez, R. Ronen, and S. Jourdan. Speculation techniques for improving load related instruction scheduling. In Proc. ISCA-26, May 1999.
-
(1999)
Proc. ISCA-26
-
-
Yoaz, A.1
Erez, M.2
Ronen, R.3
Jourdan, S.4
|