Raised source/drains for 50 nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

Solid-State Electronics

Volumn 49, Issue 4, 2005, Pages 529-534

  Waite, A M ^a   Lloyd, N S ^a   Osman, K ^a   Zhang, W ^a   Ernst, T ^b   Achard, H ^b   Wang, Y ^c   Deleonibus, S ^b   Hemment, P L F ^c   Bagnall, D M ^a   Evans, A G R ^a   Ashburn, P ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b CEA LETI   (France)

^c UNIVERSITY OF SURREY   (United Kingdom)

Author keywords

MOSFETs; Raised source drain; Selective epitaxy; Silicon epitaxy

Indexed keywords

ACTIVATION ENERGY; BINARY MIXTURES; CHEMICAL VAPOR DEPOSITION; DIFFUSION; EPITAXIAL GROWTH; PARAMETER ESTIMATION; SILANES; THRESHOLD VOLTAGE;

DICHLOROSILANE; RAISED SOURCE/DRAIN; SELECTIVE EPITAXY; SILICON EPITAXY;

MOSFET DEVICES;

EID: 13644249280     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.01.019     Document Type: Article

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