Raised source/drain (RSD) for 50nm MOSFETs - Effect of epitaxy layer thickness on short channel effects

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 223-226

  Waite, A M ^a   Lloyd, N S ^a   Ashburn, P ^a   Evans, A G R ^a   Ernst, T ^b   Achard, H ^b   Deleonibus, S ^b   Wang, Y ^c   Hemment, P ^c  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b CEA GRENOBLE   (France)

^c UNIVERSITY OF SURREY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

LAYER THICKNESS; MOSFETS; RAISED SOURCE/DRAIN; SHORT-CHANNEL EFFECT;

EID: 84907694376     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256854     Document Type: Conference Paper

References (5)

1. ITRS Roadmap, 2001.
2. R. Groziecki et. al., "Suitability of Elevated Source/ Drain for Deep Submicron CMOS", ESSDERC 1999.
3. A. Hokazono et. al., "Source/ Drain Engineering for Sub-l00nm CMOS Using Selective Epitaxial Growth Technique", IEDM 2000.
4. G. Guegan et. al., "Gate and Source/ Drain Engineering for 50nm P-Channel MOSFET", ESSDERC 2001.
5. C. Caillat et. al., "65nm Physical Gate Length NMOSFETs with Heavy Ion Implanted Pockets and Highly Reliable 2nm- Thick Gate Oxide for 1 5V Operation", VLSI Symposium, 1999.