Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 679-689

  Pomeranz, Irith ^a,b   Reddy, Sudhakar M ^a,c  

^a IEEE   (United States)

^b PURDUE UNIVERSITY   (United States)

^c UNIVERSITY OF IOWA   (United States)

Author keywords

Combinational circuits; Design for testability; Path delay faults

Indexed keywords

PATH DELAY FAULT TESTABILITY;

DELAY CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL ARITHMETIC; RANDOM PROCESSES;

COMBINATORIAL CIRCUITS;

EID: 0035473377     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953501     Document Type: Article

References (20)

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