Plasma doping technology for fabrication of nanoscale metal-oxide-semiconductor devices

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 22, Issue 6, 2004, Pages 3210-3213

  Cho, Won Ju ^a   Im, Kiju ^a   Ahn, Chang Geun ^a   Yang, Jong Heon ^a   Oh, Jihun ^a   Baek, In Bok ^a   Lee, Seongjae ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHEMICAL ACTIVATION; CRYSTAL IMPURITIES; DIELECTRIC MATERIALS; ELECTRODES; ELECTRON BEAM LITHOGRAPHY; FORMING; MOSFET DEVICES; NANOTECHNOLOGY; PHOTOLITHOGRAPHY; PLASMA APPLICATIONS; SEMICONDUCTOR DOPING; SEMICONDUCTOR INSULATOR BOUNDARIES; SILICON WAFERS; THRESHOLD VOLTAGE;

METAL GATE ELECTRODES; NANOSCALE METAL-OXIDE-SEMICONDUCTOR DEVICES; PLASMA DOPING (PLAD) TECHNOLOGY; SILICON-ON-INSULATOR (SOI) WAFER; SOURCE AND DRAIN EXTENSION(SDE);

MOS DEVICES;

EID: 13244267391     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.1813461     Document Type: Conference Paper

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