Fabrication and Process Simulation of SOI MOSFETs with a 30-nm Gate Length

Journal of the Korean Physical Society

Volumn 43, Issue 5 II, 2003, Pages 892-897

  Cho, Won Ju ^a   Yang, Jong Heon ^a   Im, Kiju ^a   Oh, Jihoon ^a   Lee, Seongjae ^a   Park, Kyoungwan ^b  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b University of Seoul   (South Korea)

Author keywords

30 nm gate; Nano MOSFET; Silumation; SOI; SPD

Indexed keywords

EID: 0344120148     PISSN: 03744884     EISSN: None     Source Type: Journal    
DOI: 10.3938/jkps.43.892     Document Type: Article

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