A signed-digit architecture for residue to binary transformation

IEEE Transactions on Computers

Volumn 46, Issue 10, 1997, Pages 1146-1150

  Pourbigharaz, F ^a,b   Yassine, H M ^c  

^a IEEE   (Canada)

^b V3 Semiconductor Corp   (Canada)

^c NONE

Author keywords

Chinese remainder theorem; Digital signal processing; Residue number systems; Residue to binary conversion; Signed digit number systems; VLSI arithmetic algorithms

Indexed keywords

ADDERS; ALGORITHMS; BINARY SEQUENCES; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; NUMBER THEORY; SET THEORY; VLSI CIRCUITS;

END AROUND CARRY (EAC) ADDITION/SUBTRACTION; RESIDUE NUMBER SYSTEMS (RNS); RESIDUE TO BINARY CONVERTER ARCHITECTURES; SINGLE DIGIT NUMBER SYSTEMS;

DIGITAL ARITHMETIC;

EID: 0031366924     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.628400     Document Type: Article

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