Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET

IEEE Transactions on Electron Devices

Volumn 52, Issue 1, 2005, Pages 23-29

  Goel, Kirti ^a   Saxena, Manoj ^b   Gupta, Mridula ^a   Gupta, R S ^a  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

Author keywords

Carrier transport efficiency; Dual material gate (DMG) epitaxial (Epi) MOSFET; SCEs (SCEs)

Indexed keywords

BOUNDARY CONDITIONS; CARRIER MOBILITY; ELECTRIC CURRENTS; ELECTRIC FIELDS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; THRESHOLD VOLTAGE;

CARRIER TRANSPORT EFFICIENCY; DUAL MATERIAL GATE (DMG) EPITAXIAL (EPI)-MOSFET; SHORT CHANNEL EFFECTS (SCE);

MOSFET DEVICES;

EID: 12344336596     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.841276     Document Type: Article

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