A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications

IEEE Transactions on Consumer Electronics

Volumn 49, Issue 1, 2003, Pages 128-134

  Hasan, M ^a   Arslan, T ^a   Thompson, J S ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

Coefficient ordering; Low power; Pipelined FFT; Switching activity

Indexed keywords

BROADCASTING; COMPUTER ARCHITECTURE; ELECTRIC POWER SUPPLIES TO APPARATUS; FAST FOURIER TRANSFORMS; LOCAL AREA NETWORKS; MOBILE COMPUTING; MULTIPLYING CIRCUITS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SWITCHING THEORY; WIRELESS TELECOMMUNICATION SYSTEMS;

MULTICARRIER SYSTEMS; POWER CONSUMING BLOCKS; POWER CONSUMPTION; SWITCHING ACTIVITY;

PIPELINE PROCESSING SYSTEMS;

EID: 0038354659     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2003.1205465     Document Type: Article

References (14)

1. J. A. C. Bingham, "Multicarrier modulation for data transmission: An idea whose time has come," IEEE Communication Magazine, vol. 36, pp. 112-117, Feb. 1998.
2. R. Van Nee and R. Prasad, "OFDM wireless multimedia communications", Artech House, Boston, 2000.
3. J. Terry and J. Heiskala, "OFDM wireless LANs: A Theoretical and Practical Guide", Sams Publisher, 2002.
4. I. S. Abu-Khater, A. Bellaouar and M. I. Elmasry., "Circuit Techniques for CMOS Low-power High-performance Multipliers", IEEE Journal of Solid-State Circuits, vol. 31, no. 10, pp. 1535-1546, Oct. 1996.
5. M. B. Bevan, "A Low-Power, High-Performance, 1024-point FFT Processor", IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 380-387, March 1999.
6. L. Jia, Y. Gao, J. Isoaho and H. Tenhunen, "A new VLSI oriented FFT algorithm and implementation", in Proceedings of Eleventh annual IEEE International ASIC conference", pp. 337-341, 1998.
7. L. Jia, Y. Gao, J. Isoaho and H. Tenhunen, "Implementation of a low power 128-point FFT processor", in Proceedings of Fifth International conference on Solid-state and Integrated Circuit Technology, pp. 369-372, 1998.
8. K.S. Stevens and B. W. Suter, "A mathematical approach to a low power FFT architecture", Proc. IEEE International symposium on Circuits and Systems, pp. II-21-II-24, 1998.
9. B. W. Hunt, K.S. Stevens, B.W. Suter and D.S. Gelosh., "A single chip low power asynchronous implementation of an FFT algorithm for space applications", Proceedings Fourth Internal symposium on advanced research in asynchronous circuits and systems, pp. 216-223, 1998.
10. K. Masselos, P. K. Merakos, R. Stouraitis and C. E. Goutis, "Novel techniques for bus power consumption reduction in realizations of Sum-of-Product computations", IEEE Transactions on Very large Scale Integration Systems, vol. 7, no. 4, December, 1999.
11. K.Masselos, S. Theoharis, P.K Merakos, T. Stouraitis and C.E.Goutis, "A novel methodology for power consumption reduction in a class of DSP algorithms", Proc. IEEE International symposium on Circuits and Systems, pp.VI-199-V-202, 1998.
12. Bi Guon and E.V.Jones, "A Pipelined FFT Processor for Word-Sequential Data", IEEE transactions on acoustics, speech, and signal processing, vol. 37, no. 12, December 1989.
13. M. Hasan and T.Arslan, "Implementation of low power FFT processor cores using a novel order based processing scheme", accepted for publication in IEE proceedings on Circuits, Devices and systems.
14. A.T. Erdogan, M. Hasan and T. Arslan, "Algorithmic low power FIR cores", accepted for publication in IEE proceedings on Circuits, Devices and systems.