Energy-aware architectures for a Real-Valued FFT implementation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 360-365

  Wang, A ^a   Chandrakasan, A P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Array signal processing; Digital signal processors; Energy efficiency; Fast Fourier transforms; Frequency domain analysis; Microsensors; Personal digital assistants; Scalability; Signal processing algorithms; Wireless sensor networks

Indexed keywords

BROADBAND NETWORKS; DESIGN; DIGITAL SIGNAL PROCESSORS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; FAST FOURIER TRANSFORMS; FREQUENCY DOMAIN ANALYSIS; LOW POWER ELECTRONICS; MICROSENSORS; NETWORK ARCHITECTURE; PERSONAL DIGITAL ASSISTANTS; POWER ELECTRONICS; POWER MANAGEMENT; SCALABILITY; SIGNAL PROCESSING; WIRELESS SENSOR NETWORKS;

ARRAY SIGNAL PROCESSING; DESIGN METHODOLOGY; ENERGY-AWARE DESIGN; MEASURED RESULTS; QUALITY REQUIREMENTS; SCALABLE APPROACH; SIGNAL PROCESSING ALGORITHMS; WORST CASE SCENARIO;

ENERGY EFFICIENCY;

EID: 1542299269     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231919     Document Type: Conference Paper

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