Techniques for leakage power reduction

Design of High-Performance Microprocessor Circuits

Volumn , Issue , 2000, Pages 46-62

  De, Vivek ^a   Ye, Yibin ^a   Keshavarzi, Ali ^a   Narendra, Siva ^a   Kao, James ^a   Somasekhar, Dinesh ^a   Nair, Raj ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Doping; Leakage current; Logic gates; P n junctions; Subthreshold current; Transistors; Tunneling

Indexed keywords

DOPING (ADDITIVES); ELECTRON TUNNELING; LOGIC GATES; SEMICONDUCTOR JUNCTIONS; TRANSISTORS;

LEAKAGE POWER REDUCTION; P-N JUNCTION; SUB-THRESHOLD CURRENT;

LEAKAGE CURRENTS;

EID: 85036634795     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470544365.ch3     Document Type: Chapter

References (24)

1. M. Bohr, et al., “A High Performance 0.25 μm Logic Technology Optimized for 1.8 V Operation,” IEDM Tech. Dig., p. 847, Dec. 1996.
2. M. Bohr, et al., “A High Performance 0.35 μm Logic Technology for 3.3 V and 2.5 V Operation,” IEDM Tech. Dig., p. 273, Dec. 1994.
3. A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Roy, and V. De, “Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction in CMOS IC’s,” 1999 Int. Symp. On Low Power Electronics and Design, p. 252, Aug. 1999.
4. A. S. Grove, Physics and Technology of Semiconductor Devices. John Wiley & Sons, New York, 1967.
5. DDq Characterization and Testing-Practical Issues,” Int. Test Conf., pp. 259-268, Oct. 1996.
6. Y. P. Tsividis, Operation and Modeling of the MOS Transistor. Mcgraw-Hill, New York, 1987.
7. J. R. Brews, “The Submicron MOSFET,” Chapter 3 in S.M. Sze, editor, High Speed Semiconductor Devices. John Wiley & Sons, New York, 1990, pp. 155-159.
8. R. F. Pierret, Semiconductor Device Fundamentals. Addison-Wesley, Reading, MA, 1996.
9. J. A. Mandelman and J. Alsmeier, “Anomalous Narrow Channel Effect in Trench-Isolated Buried-Channel p-MOSFET’s,” IEEE Elec. Dev. Ltr., vol. 15, no. 12, Dec. 1994.
10. A. Keshavarzi, K. Roy, and C. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron ICs,” Int. Test Conf., p. 146, Nov. 1997.
11. J. P. Halter and F. Najm, “A Gate-level Leakage Power Reduction Method for Ultra-low-power CMOS Circuits,” Proc. Ieee CICC 1997, pp. 475-478.
12. Y. Ye, S. Borkar, and V. De, “A New Technique for Standby Leakage Reduction in HighPerformance Circuits,” 1998 Symposium on VLSI Circuits, June 1998, pp. 40-41.
13. R. X. Gu and M. I. Elmasry, “Power Dissipation Anlaysis and Optimization of Deep Submicron CMOS Digital Circuits,” IEEE Journal on Solid-State Circuits, vol. 31, no. 5, pp. 707-713, May 1996.
14. M. C. Johnson, D. Somasekhar, and K. Roy, “Deterministic Estimation of Minimum and Maximum Leakage Conditions in CMOS Logic,” IEEE Transactions on Computer-Aided Design of IC’s, June 1999, pp. 714-725.
15. T. Kawahara, et al., “Subthreshold Current Reduction for Decoded-driver by Self-reverse Biasing,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1136-1143, Nov. 1993.
16. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE JSSC, vol. 30, no. 8, pp. 847-854, Aug. 1995.
17. J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor Sizing Issues and Tool For MultiThreshold CMOS Technology,” 34th Design Automation Conference, pp. 409-414, June 1997.
18. J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,” 35th Design Automation Conference, pp. 495-500, June 1998.
19. W. Lee, et al., “A IV DSP for Wireless Communications,” ISSCC, pp. 92-93, Feb., 1997.
20. L. Wei, Z. Chen, M. Johnson, and K. Roy, “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,” 35th Design Automation Conference, pp. 489-494, June 1998.
21. J. Kao, “Dual Threshold Voltage Domino Logic,” 25th European Solid State Circuits Conference, pp. 118-121, Sep. 1999.
22. H. C. Poon, L. D. Yau, and R. L. Johnston, “DC Model for Short-Channel IGFETs,” Intl. Electron Device Meeting, pp. 156-159, 1973.
23. K. K. Ng, S. A. Eshraghi, and T. D. Stanik, “An Improved Generalized Guide for MOSFET Scaling,” IEEE Trans. Electron Device, vol. 40, no. 10, pp. 1895-1897, Oct. 1993.
24. t Variation,” Intl. Symp. Low Power Electronics and Design, pp. 229-232, Aug. 1999.