A scalable algorithm for RTL Insertion of Gated Clocks Based on ODCs computation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 1, 2005, Pages 29-42

  Babighian, Pietro ^a   Benini, Luca ^a   Macii, Enrico ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Low power design; Low power dissipation

Indexed keywords

ALGORITHMS; DATA REDUCTION; ELECTRIC CLOCKS; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION; REDUNDANCY; SIGNAL PROCESSING;

CLOCK DISTRIBUTION NETWORKS; DESIGN COMPLEXITY; LOW POWER DESIGN; LOW-POWER DISSIPATION;

GATES (TRANSISTOR);

EID: 11844264532     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.839489     Document Type: Conference Paper

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